* Sample standard device library * * Copyright 1994-1995 by MicroSim Corporation * Neither this library nor any part may be copied without the express * written consent of MicroSim Corporation * * $Revision: 1.33 $ * $Author: rbh $ * $Date: 22 Jul 1997 16:42:58 $ * *--------------------------------------------------------------------------- * * This is a reduced version of MicroSim's standard parts libraries. Some * components from several types of component libraries have been included * here. * * * The following is a summary of parts in this library: * * Part name Part type * --------- --------- * Q2N2222 NPN bipolar transistor * Q2N2907A PNP bipolar transistor * Q2N3904 NPN bipolar transistor * Q2N3906 PNP bipolar transistor * * CD4016B Analog Switch * * D1N750 zener diode * MV2201 voltage variable capacitance diode * D1N4002 power diode * D1N4148 switching diode * MBD101 switching diode * D1N914 diode * * J2N3819 N-channel Junction field effect transistor * J2N4393 N-channel Junction field effect transistor * * IXGH40N60 N-channel Insulated Gate Bipolar Transistor * * LM324 linear operational amplifier * LF411 linear operational amplifier * UA741 linear operational amplifier * LM111 voltage comparator * * K3019PL_3C8 ferroxcube pot magnetic core * K502T300_3C8 ferroxcube pot magnetic core * K528T500_3C8 ferroxcube pot magnetic core * KRM8PL_3C8 ferroxcube pot magnetic core * * IRF150 N-type power MOS field effect transistor * IRF9140 P-type power MOS field effect transistor * * PAL20RP4B Programmable Logic Device * * A4N25 optocoupler * * 2N1595 silicon controlled rectifier * 2N5444 Triac * * 555D 555 timer subcircuit * * Sw_tOpen,Sw_tClose Time Dependent Switch Models * * P/L2C Coupled, equal, lumped T-section tline * P/L2C_A Coupled, unequal, lumped T-section tline * P/LS Uncoupled (single), lumped tline * P/T2C Coupled, equal, distributed tline * P/T2C_A Coupled,unequal,distributed(asymmetrical) tline * P/TS Uncoupled (single), distributed tline * T2COUPLED 2 symmetric coupled lossy lines * T3COUPLED 3 symmetric coupled lossy lines * * ESC2_B Pentium Mercury set IBIS I/O model * * 54152A MULTIPLEXER/DATA SELECTOR 8-1 LINE * 7400 Quadruple 2-input Positive-Nand Gates * 7401 Quadruple 2-input Positive-Nand Gates with * Open-Collector Outputs * 7402 Quadruple 2-input Positive-Nor Gates * 7403 Quadruple 2-input Positive-Nand Gates with * Open-Collector Outputs * 7404 Hex Inverters * 7405 Hex Inverters with Open-Collector Outputs * 7406 Hex Inverter Buffers/Drivers with * Open-Collector High-Voltage Outputs * 7407 Hex Buffers/Drivers with Open-Collector * High-Voltage Outputs * 7408 Quadruple 2-input Positive-And Gates * 7409 Quadruple 2-input Positive-And Gates with * Open-Collector Outputs * 7410 Triple 3-input Positive-Nand Gates * 74100 8-Bit Bistable Latches * 74107 Dual J-K Flip-Flops with Clear * 74109 Dual J-KBar Positive-Edge-Triggered Flip-Flops * 7411 Triple 3-input Posit ive-And Gates * 74S11 S-series TTL Triple 3-input Positive-AND gates * 74110 And-Gated J-K Master-Slave Flip-Flops with Data * Lockout * 74111 Dual J-K Master-Slave Flip-Flops with Data * Lockout * 7412 Triple 3-input Positive-Nand Gates with * Open-Collector Outputs * 74121 Non-retriggerable Monostable Multivibrator * w/Schmitt-Trigger Inputs * 74122 Retriggerable Monostable Multivibrator * 74123 Retriggerable Monostable Multivibrator * 74125 Quadruple Bus Buffer with 3-state Outputs * 74126 Quadruple Bus Buffer with 3-state Outputs * 74128 Line Drivers * 7413 Dual 4-input Positive-Nand Schmitt Triggers * 74132 Quadruple 2-input Positive-Nand Schmitt Trigger * 74136 Quadruple 2-input Exclusive-Or Gates with * Open-Collector Outputs * 7414 Hex Schmitt-Trigger Inverters * 74147 PRIORITY ENCODER 10-4 LINE * 74148 PRIORITY ENCODER 8-3 LINE * 74151A MULTIPLEXER/DATA SELECTOR 8-1 LINE * 74153 DUAL 4-LINE TO 1-LINE DATA * SELECTORS/MULTIPLEXERS * 74154 DECODER/DEMULTIPLEXER 4-16 LINE * 74155 DECODER/DEMULTIPLEXER 2-4 LINE * 74156 DECODER/DEMULTIPLEXER 2-4 LINE WITH * OPEN COLLECTOR OUTPUTS * 74157 QUADRUPLE 2-LINE TO 1-LINE DATA * SELECTORS/MULTIPLEXERS * 74159 DECODER/DEMULTIPLEXER 4-16 LINE WITH * OPEN-COLLECTOR OUTPUTS * 7416 Hex Inverter Buffers/Drivers with * Open-Collector High-Voltage Outputs * 74160 Synchronous 4-bit Decade Counters with * asynchronous clear * 74161 Synchronous 4-bit Binary Counter with Direct * Clear * 74162 Synchronous 4-bit Decade Counters with * synchronous clear * 74163 Synchronous 4-bit Binary Counter * 74164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS * 7417 Hex Buffers/Drivers with Open-Collector * High-Voltage Outputs * 74173 REGISTERS D-TYPE 4-BIT WITH 3-STATE OUTPUTS * 74174 HEX D-TYPE FLIP-FLOPS WITH CLEAR * 74175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR * 74176 35MHz Presettable Decade and Binary * Counter/Latch * 74177 35MHz Presettable Decade and Binary * Counter/Latch * 74178 4-BIT PARALLEL-ACCESS SHIFT REGISTER * 74179 4-BIT PARALLEL-ACCESS SHIFT REGISTER * 74180 PARITY GENERATOR/CHECKER ODD/EVEN 9-BIT * 74181 ALU / FUNCTION GENERATOR * 74182 LOOK-AHEAD CARRY GENERATOR * 74184 BCD-TO-BINARY CONVERTERS * 74185A BINARY-TO-BCD CONVERTERS * 74194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS * 74195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS * 74196 4-Bit Presettable Decade Counter/Latch * 74197 4-Bit Presettable Binary Counter/Latch * 7420 Dual 4-input Positive-Nand Gates * 7422 Dual 4-input Positive-Nand Gates with * Open-Collector Outputs * 7423 Dual 4-input Nor Gates with Strobe * 74246 DECODER/DRIVER BCD-7 SEGMENT WITH * OPEN-COLLECTOR OUTPUTS * 74248 DECODER/DRIVER BCD-7 SEGMENT WITH INTERNAL * PULLUPS * 74249 DECODER/DRIVER BCD-7 SEGMENT WITH * OPEN-COLLECTOR OUTPUTS * 7425 Dual 4-input Nor Gates with Strobe * 74251 MULTIPLEXER/DATA SELECTOR 8-1 LINE WITH * 3-STATE OUTPUTS * 74259 8-BIT ADDRESSABLE LATCHES * 7426 High-Voltage Interface Positive-Nand Gates * 74265 QUAD. COMPLEMENTARY-OUTPUT ELEMENTS * 7427 Triple 3-input Positive-Nor Gates * 74273 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH * CLEAR * 74276 QUADRUPLE J-K FLIP-FLOPS * 74278 PRIORITY REGISTERS 4-BIT CASCADABLE * 74279 QUADRUPLE SBAR-RBAR LATCHES * 7428 Quadruple 2-input Positive-Nor Buffers * 74283 4-BIT BINARY FULL ADDERS WITH FAST CARRY * 74290 COUNTER DECADE 4-BIT, ASYNCHRONOUS * 74293 COUNTER BINARY 4-BIT, ASYNCHRONOUS * 74298 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * 7430 8-input Positive-Nand Gates * 7432 Quadruple 2-input Positive-Or Gates * 7433 Quadruple 2-input Positive-Nor Buffers * w/ Open-Collector Outputs * 74351 DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE * OUTPUTS * 74365A Hex Bus Drivers with 3-STATE Outputs * 74366A Hex Bus Drivers with 3-STATE Outputs * 74367A Hex Bus Drivers with 3-STATE Outputs * 74368A Hex Bus Drivers with 3-STATE Outputs * 7437 Quadruple 2-input Positive-Nand Buffers * 74376 Quadruple J-K Flip-Flops * 7438 Quadruple 2-input Positive-Nand Buffers * w/ Open-Collector Outputs * 7439 Quadruple 2-input Positive Nand Buffers with * Open-Collector Outputs * 74390 COUNTER DECADE 4-BIT, ASYNCHRONOUS * 74393 COUNTER BINARY 4-BIT, ASYNCHRONOUS * 7440 Dual 4-input Positive-Nand Buffers * 74425 Quadruple Bus Buffers with 3-STATE Outputs * 74426 Quadruple Bus Buffers with 3-STATE Outputs * 7442A DECODER BCD-DECIMAL 4-10 LINE * 7443A DECODER EXCESS-3-DECIMAL 4-10 LINE * 7444A DECODER GRAY-DECIMAL 4-10 LINE * 7445 DECODER/DRIVER BCD-DECIMAL WITH OPEN COLLECTOR * OUTPUTS * 7446A DECODER/DRIVER BCD-7 SEGMENT WITH * OPEN-COLLECTOR OUTPUTS * 7448 DECODER/DRIVER BCD-7 SEGMENT WITH INTERNAL * PULLUPS * 7449 DECODER/DRIVER BCD-7 SEGMENT WITH * OPEN-COLLECTOR OUTPUTS * 74490 COUNTER DECADE 4-BIT, ASYNCHRONOUS * 7450 Dual 2-wide 2-input And-Or-Invert Gates * 7451 And-Or-Invert Gates * 7453 Expandable 4-wide And-Or-Invert Gates * 7454 4-wide And-Or-Invert Gates * 7460 Dual 4-input Expanders * 7470 And-Gated J-K Positive-Edge-Triggered * Flip-Flops with Preset & Clear * 7472 And Gated J-K Master-Slave * Flip-Flops with Preset and Clear * 7473 Dual J-K Flip-Flops with Clear * 7474 Dual D-Type Positive-Edge-Triggered * Flip-Flops with Preset and Clear * 7475 4-bit bistable latches (dual 2-bit common * clock4-bit bistable latches ) * 7476 Dual J-K Flip-Flops with Preset and Clear * 7477 4-bit bistable latches * 7482 2-BIT BINARY FULL ADDERS * 7483A 4-BIT BINARY FULL ADDERS WITH FAST CARRY * 7485 4-BIT MAGNITUDE COMPARATOR * 7486 Quadruple 2-input Exclusive-Or Gates * 7491A 8-BIT SHIFT REGISTERS * 7492A COUNTER DIVIDE-BY-12 4-BIT, ASYNCHRONOUS * 7493A COUNTER BINARY 4-BIT, ASYNCHRONOUS * 7494 4-BIT SHIFT REGISTERS * 7495A 4-BIT PARALLEL SHIFT REGISTERS * 7496 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS * *------------------------------------------------------------------ * Library of bipolar transistor model parameters * * This is a reduced version of MicroSim's bipolar transistor model library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in this model library were derived from the data sheets for * each part. Each part was characterized using the Parts option. * Devices can also be characterized without Parts as follows: * * NE, NC Normally set to 4 * BF, ISE, IKF These are adjusted to give the nominal beta vs. * collector current curve. BF controls the mid- * range beta. ISE/IS controls the low-current * roll-off. IKF controls the high-current rolloff. * ISC Set to ISE. * IS, RB, RE, RC These are adjusted to give the nominal VBE vs. * IC and VCE vs. IC curves in saturation. IS * controls the low-current value of VBE. RB+RE * controls the rise of VBE with IC. RE+RC controls * the rise of VCE with IC. RC is normally set to 0. * VAF Using the voltages specified on the data sheet * VAF is set to give the nominal output impedance * (RO on the .OP printout) on the data sheet. * CJC, CJE Using the voltages specified on the data sheet * CJC and CJE are set to give the nominal input * and output capacitances (CPI and CMU on the .OP * printout; Cibo and Cobo on the data sheet). * TF Using the voltages and currents specified on the * data sheet for FT, TF is adjusted to produce the * nominal value of FT on the .OP printout. * TR Using the rise and fall time circuits on the * data sheet, TR (and if necessary TF) are adjusted * to give a transient analysis which shows the * nominal values of the turn-on delay, rise time, * storage time, and fall time. * KF, AF These parameters are only set if the data sheet has * a spec for noise. Then, AF is set to 1 and KF * is set to produce a total noise at the collector * which is greater than the generator noise at the * collector by the rated number of decibels. * *$ .model Q2N2222 NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 + Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 + Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 + Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10) * National pid=19 case=TO18 * 88-09-07 bam creation *$ .model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 + Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 + Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 + Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) * National pid=63 case=TO18 * 88-09-09 bam creation *$ .model Q2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 + Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 + Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 + Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10) * National pid=23 case=TO92 * 88-09-08 bam creation *$ .model Q2N3906 PNP(Is=1.41f Xti=3 Eg=1.11 Vaf=18.7 Bf=180.7 Ne=1.5 Ise=0 + Ikf=80m Xtb=1.5 Br=4.977 Nc=2 Isc=0 Ikr=0 Rc=2.5 Cjc=9.728p + Mjc=.5776 Vjc=.75 Fc=.5 Cje=8.063p Mje=.3677 Vje=.75 Tr=33.42n + Tf=179.3p Itf=.4 Vtf=4 Xtf=6 Rb=10) * National pid=66 case=TO92 * 88-09-09 bam creation *$ *------------------------------------------------------------------------------- * Library of diode model parameters * * This is a reduced version of MicroSim's diode model library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in this model library were derived from the data sheets for * each part. Most parts were characterized using the Parts option. * Devices can also be characterized without Parts as follows: * IS nominal leakage current * RS for zener diodes: nominal small-signal impedance * at specified operating current * IB for zener diodes: set to nominal leakage current * IBV for zener diodes: at specified operating current * IBV is adjusted to give the rated zener voltage * * *** Zener Diodes *** * * "A" suffix zeners have the same parameters (e.g., 1N750A has the same * parameters as 1N750) * *$ .model D1N750 D(Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 + Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=4.7 Ibv=20.245m Nbv=1.6989 + Ibvl=1.9556m Nbvl=14.976 Tbv1=-21.277u) * Motorola pid=1N750 case=DO-35 * 89-9-18 gjg * Vz = 4.7 @ 20mA, Zz = 300 @ 1mA, Zz = 12.5 @ 5mA, Zz =2.6 @ 20mA *$ *** Voltage-variable capacitance diodes * The parameters in this model library were derived from the data sheets for * each part. Each part was characterized using the Parts option. *$ .model MV2201 D(Is=1.365p Rs=1 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=14.93p M=.4261 + Vj=.75 Fc=.5 Isr=16.02p Nr=2 Bv=25 Ibv=10u) * Motorola pid=MV2201 case=182-03 * 88-09-22 bam creation *** Switching Diodes *** *$ .model D1N4148 D(Is=2.682n N=1.836 Rs=.5664 Ikf=44.17m Xti=3 Eg=1.11 Cjo=4p + M=.3333 Vj=.5 Fc=.5 Isr=1.565n Nr=2 Bv=100 Ibv=100u Tt=11.54n) *$ .model MBD101 D(Is=192.1p Rs=.1 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=893.8f M=98.29m + Vj=.75 Fc=.5 Isr=16.91n Nr=2 Bv=5 Ibv=10u) * Motorola pid=MBD101 case=182-03 * 88-09-22 bam creation *$ *** Power Diode *** .MODEL D1N4002 D (IS=14.11E-9 N=1.984 RS=33.89E-3 IKF=94.81 XTI=3 + EG=1.110 CJO=51.17E-12 M=.2762 VJ=.3905 FC=.5 ISR=100.0E-12 + NR=2 BV=100.1 IBV=10 TT=4.761E-6) *$ *** General Purpose Fast Rectifier *** .model D1N914 D(Is=168.1E-21 N=1 Rs=.1 Ikf=0 Xti=3 Eg=1.11 Cjo=4p M=.3333 + Vj=.75 Fc=.5 Isr=100p Nr=2 Bv=100 Ibv=100u Tt=11.54n) *$ *------------------------------------------------------------------------------- * Library of junction field-effect transistor (JFET) model parameters * This is a reduced version of MicroSim's JFET model library. * You are welcome to make as many copies of it as you find convenient. * The parameters in this model library were derived from the data sheets for * each part. Each part was characterized using the Parts option. *$ .model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 + Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u + Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 + Af=1) * National pid=50 case=TO92 * 88-08-01 rmn BVmin=25 *$ .model J2N4393 NJF(Beta=9.109m Betatce=-.5 Rd=1 Rs=1 Lambda=6m Vto=-1.422 + Vtotc=-2.5m Is=205.2f Isr=1.988p N=1 Nr=2 Xti=3 Alpha=20.98u + Vk=123.7 Cgd=4.57p M=.4069 Pb=1 Fc=.5 Cgs=4.06p Kf=123E-18 + Af=1) * National pid=51 case=TO18 * 88-07-13 bam BVmin=40 *$ *------------------------------------------------------------------------------- * Library of insulated gate bipolar transistor (IGBT) model parameters * * The parameters in this model library were derived from data sheets. *This part was characterized using the Parts program and the Optimizer program. * * created using Parts release 6.3 on 12/18/95 at 16:20 .MODEL IXGH40N60 NIGBT + TAU=287.56E-9 + KP=50.034 + AREA=37.500E-6 + AGD=18.750E-6 + VT=4.1822 + KF=.36047 + CGS=31.942E-9 + COXD=53.188E-9 + VTD=2.6570 *$ *------------------------------------------------------------------------------- * Library of linear IC definitions * This is a reduced version of MicroSim's linear subcircuit library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in the opamp library were derived from the data sheets for * each part. The macromodel used is similar to the one described in: * * Macromodeling of Integrated Circuit Operational Amplifiers * by Graeme Boyle, Barry Cohn, Donald Pederson, and James Solomon * IEEE Journal of SoliE-State Circuits, Vol. SC-9, no. 6, Dec. 1974 * * Differences from the reference (above) occur in the output limiting stage * which was modified to reduce internally generated currents associated with * output voltage limiting, as well as short-circuit current limiting. * * The opamps are modelled at room temperature and do not track changes with * temperature. This library file contains models for nominal, not worst case, * devices. * *$ *----------------------------------------------------------------------------- * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt LM324 1 2 3 4 5 * c1 11 12 2.887E-12 c2 6 7 30.00E-12 dc 5 53 dx de 54 5 dx dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 21.22E6 -20E6 20E6 20E6 -20E6 ga 6 0 11 12 188.5E-6 gcm 0 6 10 99 59.61E-9 iee 3 10 dc 15.09E-6 hlim 90 0 vlim 1K q1 11 2 13 qx q2 12 1 14 qx r2 6 9 100.0E3 rc1 4 11 5.305E3 rc2 4 12 5.305E3 re1 13 10 1.845E3 re2 14 10 1.845E3 ree 10 99 13.25E6 ro1 8 5 50 ro2 7 99 25 rp 3 4 9.082E3 vb 9 0 dc 0 vc 3 53 dc 1.500 ve 54 4 dc 0.65 vlim 7 8 dc 0 vlp 91 0 dc 40 vln 0 92 dc 40 .model dx D(Is=800.0E-18 Rs=1) .model qx PNP(Is=800.0E-18 Bf=166.7) .ends *$ *----------------------------------------------------------------------------- * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt uA741 1 2 3 4 5 * c1 11 12 8.661E-12 c2 6 7 30.00E-12 dc 5 53 dx de 54 5 dx dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -10E6 10E6 10E6 -10E6 ga 6 0 11 12 188.5E-6 gcm 0 6 10 99 5.961E-9 iee 10 4 dc 15.16E-6 hlim 90 0 vlim 1K q1 11 2 13 qx q2 12 1 14 qx r2 6 9 100.0E3 rc1 3 11 5.305E3 rc2 3 12 5.305E3 re1 13 10 1.836E3 re2 14 10 1.836E3 ree 10 99 13.19E6 ro1 8 5 50 ro2 7 99 100 rp 3 4 18.16E3 vb 9 0 dc 0 vc 3 53 dc 1 ve 54 4 dc 1 vlim 7 8 dc 0 vlp 91 0 dc 40 vln 0 92 dc 40 .model dx D(Is=800.0E-18 Rs=1) .model qx NPN(Is=800.0E-18 Bf=93.75) .ends *$ *----------------------------------------------------------------------------- * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt LF411 1 2 3 4 5 * c1 11 12 4.196E-12 c2 6 7 10.00E-12 css 10 99 1.333E-12 dc 5 53 dx de 54 5 dx dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 31.83E6 -30E6 30E6 30E6 -30E6 ga 6 0 11 12 251.4E-6 gcm 0 6 10 99 2.514E-9 iss 10 4 dc 170.0E-6 hlim 90 0 vlim 1K j1 11 2 10 jx j2 12 1 10 jx r2 6 9 100.0E3 rd1 3 11 3.978E3 rd2 3 12 3.978E3 ro1 8 5 50 ro2 7 99 25 rp 3 4 15.00E3 rss 10 99 1.176E6 vb 9 0 dc 0 vc 3 53 dc 1.500 ve 54 4 dc 1.500 vlim 7 8 dc 0 vlp 91 0 dc 25 vln 0 92 dc 25 .model dx D(Is=800.0E-18 Rs=1m) .model jx NJF(Is=12.50E-12 Beta=743.3E-6 Vto=-1) .ends *$ *----------------------------------------------------------------------------- *** Voltage comparators * The parameters in this comparator library were derived from data sheets for * each parts. The macromodel used was developed by MicroSim Corporation, and * is produced by the "Parts" option to PSpice. * * Although we do not use it, another comparator macro model is described in: * * An Integrated-Circuit Comparator Macromodel * by Ian Getreu, Andreas Hadiwidjaja, and Johan Brinch * IEEE Journal of Solid-State Circuits, Vol. SC-11, no. 6, Dec. 1976 * * This reference covers the considerations that go into duplicating the * behavior of voltage comparators. * * The comparators are modelled at room temperature. The macro model does not * track changes with temperature. This library file contains models for * nominal, not worst case, devices. * *$ *----------------------------------------------------------------------------- * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | open collector output * | | | | | output ground * | | | | | | .subckt LM111 1 2 3 4 5 6 * f1 9 3 v1 1 iee 3 7 dc 100.0E-6 vi1 21 1 dc .45 vi2 22 2 dc .45 q1 9 21 7 qin q2 8 22 7 qin q3 9 8 4 qmo q4 8 8 4 qmi .model qin PNP(Is=800.0E-18 Bf=833.3) .model qmi NPN(Is=800.0E-18 Bf=1002) .model qmo NPN(Is=800.0E-18 Bf=1000 Cjc=1E-15 Tr=118.8E-9) e1 10 6 9 4 1 v1 10 11 dc 0 q5 5 11 6 qoc .model qoc NPN(Is=800.0E-18 Bf=34.49E3 Cjc=1E-15 Tf=364.6E-12 Tr=79.34E-9) dp 4 3 dx rp 3 4 6.122E3 .model dx D(Is=800.0E-18 Rs=1) * .ends *$ *------------------------------------------------------------------------------- * Library of magnetic core model parameters * This is a reduced version of MicroSim's magnetic core library. * You are welcome to make as many copies of it as you find convenient. * The parameters in this model library were derived from the data sheets for * each core. The Jiles-Atherton magnetics model is described in: * * Theory of Ferromagnetic Hysteresis, by D C Jiles and D L Atherton, * Journal of Magnetism and Magnetic Materials, vol 61 (1986) pp 48-60 * * Model parameters for ferrite material (Ferroxcube 3C8) were obtained by * trial simulations, using the B-H curves from the manufacturer's catalog. * Then, the library was compiled from the data sheets for each core geometry. * Notice that only the geometric values change once a material is * characterized. * Example use: K2 L2 .99 K1409PL_3C8 * Notes: * 1) Using a K device (formerly only for mutual coupling) with a model * reference changes the meaning of the L device: the inductance value * becomes the number of turns for the winding. * 2) K devices can "get away" with specifying only one inductor, as in the * example above, to simulate power inductors. * Example circuit file: *+----------------------------------------------------------------------------- *|Demonstration of power inductor B-H curve *| *|* To view results with Probe (B-H curve): *|* 1) Add Trace for B(K1) *|* 2) set X-axis variable to H(K1) *|* *|* Probe x-axis unit is Oersted *|* Probe y-axis unit is Gauss *|* *|.tran .1 4 *|igen0 0 1 sin(0 .1amp 1Hz 0) ; Generator: starts with 0.1 amp sinewave, then *|igen1 0 1 sin(0 .1amp 1Hz 1) ; +0.1 amps, starting at 1 second *|igen2 0 1 sin(0 .2amp 1Hz 2) ; +0.2 amps, starting at 2 seconds *|igen3 0 1 sin(0 .8amp 1Hz 3) ; +0.4 amps, starting at 3 seconds *|RL 1 0 1ohm ; generator source resistance *|L1 1 0 20 ; inductor with 20 turns *|K1 L1 .9999 K528T500_3C8 ; Ferroxcube torroid core *|.model K528T500_3C8 CORE(Ms=415.2K A=44.82 C=.4112 K=25.74) *|+ AREA=1.17 PATH=8.49) *|.options itl5=0 *|.probe *|.end *+----------------------------------------------------------------------------- *** Ferroxcube pot cores: 3C8 material *$ .model K3019PL_3C8 Core(MS=415.2K A=44.82 C=.4112 K=25.74 + Area=1.38 Path=4.52) *** Ferroxcube square cores: 3C8 material *$ .model KRM8PL_3C8 Core(MS=415.2K A=44.82 C=.4112 K=25.74 + Area=.630 Path=3.84) *** Ferroxcube toroid cores: 3C8 material *$ .model K502T300_3C8 Core(MS=415.2K A=44.82 C=.4112 K=25.74 + Area=.371 Path=7.32) *$ .model K528T500_3C8 Core(MS=415.2K A=44.82 C=.4112 K=25.74 + Area=1.17 Path=8.49) *$ *------------------------------------------------------------------------------- * Library of MOSFET model parameters (for "power" MOSFET devices) * * This is a reduced version of MicroSim's power MOSFET model library. * You are welcome to make as many copies of it as you find convenient. * * The parameters in this model library were derived from the data sheets for * each part. Each part was characterized using the Parts option. * Device can also be characterized without Parts as follows: * LEVEL Set to 3 (short-channel device). * TOX Determined from gate ratings. * L, LD, W, WD Assume L=2u. Calculate from input capacitance. * XJ, NSUB Assume usual technology. * IS, RD, RB Determined from "source-drain diode forward voltage" * specification or curve (Idr vs. Vsd). * RS Determine from Rds(on) specification. * RDS Calculated from Idss specification or curves. * VTO, UO, THETA Determined from "output characteristics" curve family * (Ids vs. Vds, stepped Vgs). * ETA, VMAX, CBS Set for null effect. * CBD, PB, MJ Determined from "capacitance vs. Vds" curves. * RG Calculate from rise/fall time specification or curves. * CGSO, CGDO Determined from gate-charge, turn-on/off delay and * rise time specifications. * * NOTE: when specifying the instance of a device in your circuit file: * * BE SURE to have the source and bulk nodes connected together, as this * is the way the real device is constructed. * * DO NOT include values for L, W, AD, AS, PD, PS, NRD, or NDS. * The PSpice default values for these parameters are taken into account * in the library model statements. Of course, you should NOT reset * the default values using the .OPTIONS statement, either. * * Example use: M17 15 23 7 7 IRF150 * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * The "power" MOSFET device models benefit from relatively complete specifi- * cation of static and dynamic characteristics by their manufacturers. The * following effects are modeled: * - DC transfer curves in forward operation, * - gate drive characteristics and switching delay, * - "on" resistance, * - reverse-mode "body-diode" operation. * * The factors not modeled include: * - maximum ratings (eg. high-voltage breakdown), * - safe operating area (eg. power dissipation), * - latch-up, * - noise. * * For high-current switching applications, we advise that you include * series inductance elements, for the source and drain, in your circuit file. * In doing so, voltage spikes due to di/dt will be modeled. According to the * 1985 International Rectifier databook, the following case styles have lead * inductance values of: * TO-204 (modified TO-3) source = 12.5nH drain = 5.0nH * TO-220 source = 7.5nH drain = 3.5-4.5nH * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *$ .model IRF150 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=1.624m Kp=20.53u W=.3 L=2u Vto=2.831 + Rd=1.031m Rds=444.4K Cbd=3.229n Pb=.8 Mj=.5 Fc=.5 Cgso=9.027n + Cgdo=1.679n Rg=13.89 Is=194E-18 N=1 Tt=288n) * Int'l Rectifier pid=IRFC150 case=TO3 * 88-08-25 bam creation *$ .model IRF9140 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0 Vmax=0 Xj=0 + Tox=100n Uo=300 Phi=.6 Rs=70.6m Kp=10.15u W=1.9 L=2u Vto=-3.67 + Rd=60.66m Rds=444.4K Cbd=2.141n Pb=.8 Mj=.5 Fc=.5 Cgso=877.2p + Cgdo=369.3p Rg=.811 Is=52.23E-18 N=2 Tt=140n) * Int'l Rectifier pid=IRFC9140 case=TO3 * 88-08-25 bam creation *$ *-------------------------------------------------------------------- * Digital Components * *------------------------------------------------------------------------- *$ * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7400 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_00 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_00 ugate ( + tplhty=11ns tplhmx=22ns + tphlty=7ns tphlmx=15ns + ) *--------- *$ * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7401 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_01 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_01 ugate ( + tplhty=35ns tplhmx=55ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7402 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_02 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_02 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7403 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7403 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_03 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_03 ugate ( + tplhty=35ns tplhmx=45ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7404 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7404 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_04 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_04 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7405 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7405 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_05 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_05 ugate ( + tplhty=40ns tplhmx=55ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7406 Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7406 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_06 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_06 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=15ns tphlmx=23ns + ) *-------- *$ * 7407 Hex Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7407 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_07 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_07 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=20ns tphlmx=30ns + ) *-------- *$ * 7408 Quadruple 2-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7408 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_08 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_08 ugate ( + tplhty=17.5ns tplhmx=27ns + tphlty=12ns tphlmx=19ns + ) *--------- *$ * 7409 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7409 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_09 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_09 ugate ( + tplhty=21ns tplhmx=32ns + tphlty=16ns tphlmx=24ns + ) *--------- *$ * 7410 Triple 3-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7410 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_10 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_10 ugate ( + tplhty=11ns tplhmx=22ns + tphlty=7ns tphlmx=15ns + ) *-------- *$ * 7411 Triple 3-input Positive-And Gates * * 1989 National Semiconductor * .subckt 7411 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_11 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_11 ugate ( + tplhmx=27ns + tphlmx=19ns + ) *-------- *$ * 7412 Triple 3-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7412 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_12 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_12 ugate ( + tplhty=35ns tplhmx=45ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7413 Dual 4-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7413 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled in the AtoD interface U1 nand(4) DPWR DGND + A B C D Y + D_13 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_13 ugate ( + tplhty=18ns tplhmx=27ns + tphlty=15ns tphlmx=22ns + ) *--------- *$ * 7414 Hex Schmitt-Trigger Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7414 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface U1 inv DPWR DGND + A Y + D_14 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_14 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *--------- *$ * 7416 Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7416 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_16 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_16 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=15ns tphlmx=23ns + ) *-------- *$ * 7417 Hex Buffers/Drivers with Open-Collector High-Voltage Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7417 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_17 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_17 ugate ( + tplhty=6ns tplhmx=10ns + tphlty=20ns tphlmx=30ns + ) *--------- *$ * 7420 Dual 4-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7420 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_20 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_20 ugate ( + tplhty=12ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7422 Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7422 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_22 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_22 ugate ( + tplhty=35ns tplhmx=45ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7423 Dual 4-input Nor Gates with Strobe * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7423 1A 1B 1C 1D 1G X XBAR 1Y 2A 2B 2C 2D 2G 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * * The x and xbar inputs of this gate should only come from the following * gates: * '60 * * PSpice, however, will not check that it is properly connected. UIBUF bufa(2) DPWR DGND + 1G 2G 1G_BUF 2G_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + XBAR XBARC + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U11 aoi(2,5) DPWR DGND + 1A 1G_BUF + 1B 1G_BUF + 1C 1G_BUF + 1D 1G_BUF + X XBARC + 1Y + D_23 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U21 aoi(2,4) DPWR DGND + 2A 2G_BUF 2B 2G_BUF 2C 2G_BUF 2D 2G_BUF 2Y + D_23 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_23 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7425 Dual 4-input Nor Gates with Strobe * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7425 A B C D G Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(4) DPWR DGND + A B C D X + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 nand(2) DPWR DGND + X G Y + D_25 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_25 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *-------- *$ * 7426 High-Voltage Interface Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7426 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_26 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_26 ugate ( + tplhty=16ns tplhmx=24ns + tphlty=11ns tphlmx=17ns + ) *--------- *$ * 7427 Triple 3-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7427 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_27 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_27 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=7ns tphlmx=11ns + ) *--------- *$ * 7428 Quadruple 2-input Positive-Nor Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7428 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_28 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_28 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=8ns tphlmx=12ns + ) *--------- *$ * 7430 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7430 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_30 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_30 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7432 Quadruple 2-input Positive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7432 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_32 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_32 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=14ns tphlmx=22ns + ) *--------- *$ * 7433 Quadruple 2-input Positive-Nor Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7433 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_33 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_33 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=12ns tphlmx=18ns + ) *--------- *$ * 7437 Quadruple 2-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7437 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_37 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_37 ugate ( + tplhty=13ns tphlty=8ns + tplhmx=22ns tphlmx=15ns + ) *--------- *$ * 7438 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7438 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_38 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_38 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=11ns tphlmx=18ns + ) *--------- *$ * 7439 Quadruple 2-input Positive Nand Buffers with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/10/89 Update interface and model names .subckt 7439 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_39 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_39 ugate ( + tphlmx=18ns tplhmx=22ns + ) *--------- *$ * 7440 Dual 4-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names .subckt 7440 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_40 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_40 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7442A DECODER BCD-DECIMAL 4-10 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-30-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7442A A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U42ALOG LOGICEXP (4,14) DPWR DGND + A_I B_I C_I D_I + A B C D + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + DBAR = { ~D } + Y0 = { ~(DBAR & CBAR & BBAR & ABAR ) } + Y1 = { ~(DBAR & CBAR & BBAR & A ) } + Y2 = { ~(DBAR & CBAR & B & ABAR ) } + Y3 = { ~(DBAR & CBAR & B & A ) } + Y4 = { ~(DBAR & C & BBAR & ABAR ) } + Y5 = { ~(DBAR & C & BBAR & A ) } + Y6 = { ~(DBAR & C & B & ABAR ) } + Y7 = { ~(DBAR & C & B & A ) } + Y8 = { ~(D & CBAR & BBAR & ABAR ) } + Y9 = { ~(D & CBAR & BBAR & A ) } U42ADLY PINDLY (10,0,4) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + A B C D + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC = { CHANGED(C,0) } + ADDRD = { CHANGED(D,0) } + + PINDLY: + Y0_O = { + CASE ( + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,14NS,25NS) + ) + } + Y1_O = { + CASE ( + ADDRA , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y2_O = { + CASE ( + ADDRB , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y3_O = { + CASE ( + ADDRA | ADDRB , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y4_O = { + CASE ( + ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y5_O = { + CASE ( + ADDRA | ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y6_O = { + CASE ( + ADDRB | ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y7_O = { + CASE ( + ADDRA | ADDRB | ADDRC, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y8_O = { + CASE ( + ADDRD , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y9_O = { + CASE ( + ADDRA | ADDRD, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } .ENDS *-------- *$ * 7443A DECODER EXCESS-3-DECIMAL 4-10 LINE * * THE TTL DATA BOOK, VOLUME 2, STANDARD, S, LS, TTL; TI, 1985 * JLS 7-30-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7443A A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U43ALOG LOGICEXP (4,14) DPWR DGND + A_I B_I C_I D_I + A B C D + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + DBAR = { ~D } + Y0 = { ~(DBAR & CBAR & B & A ) } + Y1 = { ~(DBAR & C & BBAR & ABAR ) } + Y2 = { ~(DBAR & C & BBAR & A ) } + Y3 = { ~(DBAR & C & B & ABAR ) } + Y4 = { ~(DBAR & C & B & A ) } + Y5 = { ~(D & CBAR & BBAR & ABAR ) } + Y6 = { ~(D & CBAR & BBAR & A ) } + Y7 = { ~(D & CBAR & B & ABAR ) } + Y8 = { ~(D & CBAR & B & A ) } + Y9 = { ~(D & C & BBAR & ABAR ) } U43ADLY PINDLY (10,0,4) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + A B C D + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC = { CHANGED(C,0) } + ADDRD = { CHANGED(D,0) } + + PINDLY: + Y0_O = { + CASE ( + ADDRA | ADDRB , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y1_O = { + CASE ( + ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y2_O = { + CASE ( + ADDRA | ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y3_O = { + CASE ( + ADDRB | ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y4_O = { + CASE ( + ADDRA | ADDRB | ADDRC, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y5_O = { + CASE ( + ADDRD , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y6_O = { + CASE ( + ADDRA | ADDRD , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y7_O = { + CASE ( + ADDRB | ADDRD , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y8_O = { + CASE ( + ADDRA | ADDRB | ADDRD, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y9_O = { + CASE ( + ADDRC | ADDRD , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } .ENDS *--------- *$ * 7444A DECODER GRAY-DECIMAL 4-10 LINE * * THE TTL DATA BOOK, VOLUME 2, STANDARD, S, LS, TTL; 1985, TI * JLS 7-30-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7444A A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U44ALOG LOGICEXP (4,14) DPWR DGND + A_I B_I C_I D_I + A B C D + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + DBAR = { ~D } + Y0 = { ~(DBAR & CBAR & B & ABAR ) } + Y1 = { ~(DBAR & C & B & ABAR ) } + Y2 = { ~(DBAR & C & B & A ) } + Y3 = { ~(DBAR & C & BBAR & A ) } + Y4 = { ~(DBAR & C & BBAR & ABAR ) } + Y5 = { ~(D & C & BBAR & ABAR ) } + Y6 = { ~(D & C & BBAR & A ) } + Y7 = { ~(D & C & B & A ) } + Y8 = { ~(D & C & B & ABAR ) } + Y9 = { ~(D & CBAR & B & ABAR ) } U44ADLY PINDLY (10,0,4) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + A B C D + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC = { CHANGED(C,0) } + ADDRD = { CHANGED(D,0) } + + PINDLY: + Y0_O = { + CASE ( + ADDRB , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y1_O = { + CASE ( + ADDRB | ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y2_O = { + CASE ( + ADDRA | ADDRB | ADDRC, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y3_O = { + CASE ( + ADDRA | ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y4_O = { + CASE ( + ADDRC , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y5_O = { + CASE ( + ADDRC | ADDRD , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y6_O = { + CASE ( + ADDRA | ADDRC | ADDRD, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y7_O = { + CASE ( + ADDRA | ADDRB | ADDRC | ADDRD, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y8_O = { + CASE ( + ADDRB | ADDRC | ADDRD, DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } + Y9_O = { + CASE ( + ADDRB | ADDRD , DELAY(-1,17NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,25NS), + DELAY(-1,17NS,30NS) + ) + } .ENDS *--------- *$ * 7445 DECODER/DRIVER BCD-DECIMAL WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7445 A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 X1 A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O DPWR DGND 74145 + PARAMS: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS *-------- *$ * 7446A DECODER/DRIVER BCD-7 SEGMENT WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7446A INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 X1 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O DPWR DGND 7447A + PARAMS: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS *--------- *$ * 7447A DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7447A INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 OR(6) DPWR DGND + LT RBIBAR INA INB INC IND + BIBAR/RBOBAR_B + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} U47ALOG LOGICEXP (7,13) DPWR DGND + INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + INA INB INC IND RBIBAR LT + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + RBIBAR = { RBIBAR_I } + LTBAR = { LTBAR_I } + BIBAR/RBOBAR = { BIBAR/RBOBAR_B } + + LT = { ~LTBAR } + ALT = { ~(INA & LTBAR) } + BLT = { ~(INB & LTBAR) } + CLT = { ~(INC & LTBAR) } + DLT = { ~IND } + ABI = { ~(ALT & BIBAR/RBOBAR) } + BBI = { ~(BLT & BIBAR/RBOBAR) } + CBI = { ~(CLT & BIBAR/RBOBAR) } + DBI = { ~(DLT & BIBAR/RBOBAR) } + + OUTA = { (BBI & DBI) | (ALT & CBI) | (ABI & BLT & CLT & DLT) } + OUTB = { (BBI & DBI) | (ABI & BLT & CBI) | (ALT & BBI & CBI) } + OUTC = { (CBI & DBI) | (ALT & BBI & CLT) } + OUTD = { (ABI & BLT & CLT) | (ALT & BLT & CBI) | (ABI & BBI & CBI) } + OUTE = { ABI | (BLT & CBI) } + OUTF = { (ABI & BBI) | (BBI & CLT) | (ABI & CLT & DLT) } + OUTG = { (ABI & BBI & CBI) | (BLT & CLT & DLT & LTBAR) } U47ADLY_OC PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_STD_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } .ENDS *--------- *$ * 7448 DECODER/DRIVER BCD-7 SEGMENT WITH INTERNAL PULLUPS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7448 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 OR(6) DPWR DGND + LT RBIBAR INA INB INC IND + BIBAR/RBOBAR_B + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} U48LOG LOGICEXP (7,13) DPWR DGND + INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + INA INB INC IND RBIBAR LT + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + RBIBAR = { RBIBAR_I } + LTBAR = { LTBAR_I } + BIBAR/RBOBAR = { BIBAR/RBOBAR_B } + + LT = { ~LTBAR } + ALT = { ~(INA & LTBAR) } + BLT = { ~(INB & LTBAR) } + CLT = { ~(INC & LTBAR) } + DLT = { ~IND } + ABI = { ~(ALT & BIBAR/RBOBAR) } + BBI = { ~(BLT & BIBAR/RBOBAR) } + CBI = { ~(CLT & BIBAR/RBOBAR) } + DBI = { ~(DLT & BIBAR/RBOBAR) } + + OUTA = { ~((BBI & DBI) | (ALT & CBI) | (ABI & BLT & CLT & DLT)) } + OUTB = { ~((BBI & DBI) | (ABI & BLT & CBI) | (ALT & BBI & CBI)) } + OUTC = { ~((CBI & DBI) | (ALT & BBI & CLT)) } + OUTD = { ~((ABI & BLT & CLT) | (ALT & BLT & CBI) | (ABI & BBI & CBI)) } + OUTE = { ~( ABI | (BLT & CBI)) } + OUTF = { ~((ABI & BBI) | (BBI & CLT) | (ABI & CLT & DLT)) } + OUTG = { ~((ABI & BBI & CBI) | (BLT & CLT & DLT & LTBAR)) } U48DLY PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } .ENDS *--------- *$ * 7449 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7449 INA_I INB_I INC_I IND_I BIBAR_I + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U49LOG LOGICEXP (5,7) DPWR DGND + INA_I INB_I INC_I IND_I BIBAR_I + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + BIBAR = { BIBAR_I } + + ABAR = { ~INA } + BBAR = { ~INB } + CBAR = { ~INC } + DBAR = { ~IND } + ABI = { ~(ABAR & BIBAR) } + BBI = { ~(BBAR & BIBAR) } + CBI = { ~(CBAR & BIBAR) } + DBI = { ~(DBAR & BIBAR) } + + OUTA = { ~((BBI & DBI) | (ABAR & CBI) | (ABI & BBAR & CBAR & DBAR)) } + OUTB = { ~((BBI & DBI) | (ABI & BBAR & CBI) | (ABAR & BBI & CBI)) } + OUTC = { ~((CBI & DBI) | (ABAR & BBI & CBAR)) } + OUTD = { ~((ABI & BBAR & CBAR) | (ABAR & BBAR & CBI) | + (ABI & BBI & CBI)) } + OUTE = { ~( ABI | (BBAR & CBI)) } + OUTF = { ~((ABI & BBI) | (BBI & CBAR) | (ABI & CBAR & DBAR)) } + OUTG = { ~((ABI & BBI & CBI) | (BBAR & CBAR & DBAR)) } U49DLY_OC PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_STD_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } .ENDS *--------- *$ * 7450 Dual 2-wide 2-input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7450 1A 1B 1C 1D X XBAR 1Y 2A 2B 2C 2D 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x and xbar inputs of gate 1 of this chip can only come from the * following gates: * '50 * '60 * PSpice, however, will not check that these are properly connected. U1V inv DPWR DGND + XBAR XBARC + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 aoi(2,3) DPWR DGND + 1A 1B 1C 1D X XBARC 1Y + D_50_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + 2A 2B 2C 2D 2Y + D_50_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_50_1 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7451 And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7451 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,2) DPWR DGND + A B C D Y + D_51 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_51 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7453 Expandable 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7453 A B C D E F G H X XBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * The x and xbar inputs of this gate should only come from the following * chips: * '60 * '62 * PSpice, however, will not check that these are properly connected. U1 inv DPWR DGND + XBAR XBARC + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 aoi(2,5) DPWR DGND + A B + C D + E F + G H + X XBARC + Y + D_53 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_53 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7454 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names .subckt 7454 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(2,4) DPWR DGND + A B C D E F G H Y + D_54 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_54 ugate ( + tplhty=13ns tplhmx=22ns + tphlty=8ns tphlmx=15ns + ) *--------- *$ * 7460 Dual 4-input Expanders * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7460 A B C D X XBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --- NOTE --- * this gate should only be connected to the following expandable gates: * '23 * '50 * '53 * connected by both x and xbar connections * PSpice, however, will not check that these are correctly connected. * ALSO this gate has no propagation delay. * There is a total propagation delay in the last level NOR gate in the * above chips, so when properly connected, the expanded combination will * work correctly. U1 and(4) DPWR DGND + A B C D X + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + X XBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} .ends *--------- *$ * 7470 And-Gated J-K Positive-Edge-Triggered Flip-Flops with Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7470 CLK PREBAR CLRBAR J1 J2 JBAR K1 K2 KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1V inva(3) DPWR DGND + CLK JBAR KBAR CLKBAR J3 K3 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2A anda(3,2) DPWR DGND + J3 J1 J2 K3 K1 K2 J K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 jkff(1) DPWR DGND + PREBAR CLRBAR CLKBAR J K Q QBAR + D_70 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_70 ueff ( + tppcqlhmx=50ns tppcqhlmx=50ns + tpclkqlhty=27ns tpclkqlhmx=50ns + tpclkqhlty=18ns tpclkqhlmx=50ns + twclkhmx=20ns twclkhty=20ns + twclklmx=30ns twclklty=30ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkmn=20ns + thdclkmx=5ns thdclkmn=5ns + ) *-------- *$ * 7472 And Gated J-K Master-Slave Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/11/89 Update interface and model names .subckt 7472 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + PREBAR CLRBAR PREB CLRB + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 buf DPWR DGND + CLK CLK_BUF + D_72_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 anda(3,2) DPWR DGND + J1 J2 J3 K1 K2 K3 J K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U4 inva(3) DPWR DGND + J K CLK_BUF JB KB CLKB + D0_GATE IO_STD UF1 srff(1) DPWR DGND + PREB CLRB CLK_BUF W1 W2 Y YB + D_72_2 IO_STD MNTYMXDLY={MNTYMXDLY} UF2 srff(1) DPWR DGND + PREB CLRB CLKB Y YB Q1 QB1 + D_72_3 IO_STD MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J K QBD J KB $D_HI W1 + D_72_4 IO_STD U6 ao(3,2) DPWR DGND + J K QD JB K $D_HI W2 + D_72_4 IO_STD U7 bufa(4) DPWR DGND + Q1 Q1 QB1 QB1 Q QD QBAR QBD + D_72_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_72_1 ugate ( + tplhty=6ns tplhmx=6ns + ) .model D_72_2 ugff ( + twghmn=20ns twpclmn=25ns + ) .model D_72_3 ugff ( + twghmn=47ns twpclmn=25ns + tppcqhlty=19ns tppcqhlmx=34ns + tppcqlhty=10ns tppcqlhmx=19ns + tpgqlhty=10ns tpgqlhmx=19ns + tpgqhlty=19ns tpgqhlmx=34ns + ) .model D_72_4 ugate ( + tphlty=6ns tphlmx=6ns + tplhty=6ns tplhmx=6ns + ) *--------- *$ * 7473 Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7473 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + CLRBAR J K CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2BUF buf DPWR DGND + CLK CLK_BUF + D_73_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_STD U2A ao(3,2) DPWR DGND + J_BUF QBAR_BUFD K_BUF J_BUF KB $D_HI W1 + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} U2B ao(3,2) DPWR DGND + J_BUF K_BUF Q_BUFD $D_HI JB K_BUF W2 + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} U3 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLK_BUF W1 W2 Y YB + D_73_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 srff(1) DPWR DGND + $D_HI CLRBAR_BUF CLKBAR Y YB QBUF QBAR_BUF + D_73_2 IO_STD MNTYMXDLY={MNTYMXDLY} UOBUF bufa(2) DPWR DGND + QBUF QBAR_BUF Q QBAR + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UBUF bufa(2) DPWR DGND + QBUF QBAR_BUF Q_BUFD QBAR_BUFD + D_73_3 IO_STD MNTYMXDLY={MNTYMXDLY} .ends .model D_73_1 ugff ( + twghmx=14ns twghty=14ns + twpclmx=25ns twpclty=25ns + ) .model D_73_2 ugff ( + tppcqlhty=10ns tppcqlhmx=19ns + tppcqhlty=19ns tppcqhlmx=34ns + tpgqlhty=10ns tpgqlhmx=19ns + tpgqhlty=19ns tpgqhlmx=34ns + twghmx=47ns twghty=47ns + twpclmx=25ns twpclty=25ns + ) .model D_73_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) .model D_73_4 ugate ( + tplhmn=6ns tplhmx=6ns + ) *--------- *$ * 7474 Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7474 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_74 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_74 ueff ( + twpclmn=30ns twclklmn=37ns + twclkhmn=30ns tsudclkmn=20ns + thdclkmn=5ns tppcqlhmx=25ns + tppcqhlmx=40ns tpclkqlhty=14ns + tpclkqlhmx=25ns tpclkqhlty=20ns + tpclkqhlmx=40ns + ) *--------- *$ * 7475 4-bit bistable latches (dual 2-bit common clock4-bit bistable latches ) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7475 1D 2D C 1Q 1QBAR 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + 1D 2D C 1D_BUF 2D_BUF C_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U12 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF 1Q 2Q $D_NC $D_NC + D_75_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12B dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF $D_NC $D_NC 1QBAR 2QBAR + D_75_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_75_1 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=16ns + tpdqlhmx=30ns tpdqhlty=14ns + tpdqhlmx=25ns + ) .model D_75_2 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=24ns + tpdqlhmx=40ns tpdqhlty=7ns + tpdqhlmx=15ns + ) *--------- *$ * 7476 Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * jgt 09/09/96 Changed to use JKFF's rather than SRFF's, and * added constraint checking. .subckt 7476 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * --NOTE-- * The standard Flip-Flops are pulse triggered * * UIBUF bufa(7) DPWR DGND + PREBAR CLRBAR J K CLK Q2 QB2 + PREBAR_BUF CLRBAR_BUF J_BUF K_BUF CLK_BUF Q QBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UE1 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLK_BAR J_BUF K_BUF Y YB + D_76_0 IO_STD MNTYMXDLY={MNTYMXDLY} UE2 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLK_BUF Y YB Q2 QB2 + D_76_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2BUF inv DPWR DGND + CLK_BUF CLK_BAR + D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U116CON CONSTRAINT(5) DPWR DGND + CLK PREBAR CLRBAR J K + IO_STD + + WIDTH: + NODE = CLRBAR + MIN_LO = 18NS + MIN_HI = 18NS + + WIDTH: + NODE = CLK + MIN_LO = 47NS + MIN_HI = 20NS + + WIDTH: + NODE = PREBAR + MIN_LO = 25NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 25NS + + GENERAL: + WHEN = { CLK=='1 & (CHANGED(J,0NS) | CHANGED(K,0NS)) } + MESSAGE = "J AND K INPUTS MUST BE STABLE WHEN CLK IS HIGH" * .ends * .model D_76_0 ueff () .model D_76_1 ueff ( + tppcqlhty=16ns tppcqlhmx=25ns + tppcqhlty=25ns tppcqhlmx=40ns + tpclkqlhty=16ns tpclkqlhmx=25ns + tpclkqhlty=25ns tpclkqhlmx=40ns + ) *--------- *$ * 7477 4-bit bistable latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names .subckt 7477 1D 2D C 1Q 2Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * There are actually 2 2-bit latches(per 1 control) in the real IC. The model * here for the IC contains only 1 2-bit latches. If 4-bit latches is needed, * please use the SUBCKT twice. UIBUF buf DPWR DGND + C C_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D 2D 1Q 2Q $D_NC $D_NC + D_77 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_77 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=16ns + tpdqlhmx=30ns tpdqhlty=14ns + tpdqhlmx=25ns + ) *--------- *$ * 7482 2-BIT BINARY FULL ADDERS * * THE TTL DATA BOOK, VOL 2, STANDARD, S, LS, TTL, 1985, TI * NH 8/25/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * SINCE THE PROP DELAY FROM A1/B1 TO SUM1 IS NOT GIVEN, THE PROP DELAY * FROM B2 TO SUM2 WILL BE USED AS THE PROP DELAY FROM Ai/Bi TO SUMi & C2 .SUBCKT 7482 C0_I A1_I B1_I A2_I B2_I SUM1_O SUM2_O C2_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U82LOG LOGICEXP(5,8) DPWR DGND + C0_I A1_I B1_I A2_I B2_I + C0 A1 B1 A2 B2 SUM1 SUM2 C2 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} + + LOGIC: + C0 = { C0_I } + A1 = { A1_I } + B1 = { B1_I } + A2 = { A2_I } + B2 = { B2_I } + A2BAR = { ~A2 } + B2BAR = { ~B2 } + + C0A1B1 = { ~( (C0 & A1) | (C0 & B1) | (A1 & B1) ) } + SUM1 = { (C0 & C0A1B1) | (A1 & C0A1B1) | (B1 & C0A1B1) | (C0 & A1 & B1) } + C2 = { ~( ( C0A1B1 & A2BAR) | (C0A1B1 & B2BAR) | (A2BAR & B2BAR) ) } + SUM2 = { ~( (C0A1B1 & C2) | (C2 & A2BAR) | (C2 & B2BAR) | + (A2BAR & B2BAR & C0A1B1) ) } U82DLY PINDLY(3,0,5) DPWR DGND + SUM1 SUM2 C2 + C0 A1 B1 A2 B2 + SUM1_O SUM2_O C2_O + IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ANY_CH_AB = { CHANGED(A2,0) | CHANGED(B2,0) | CHANGED(A1,0) | CHANGED(B1,0) } + + PINDLY: + SUM1_O = { + CASE( + CHANGED(C0,0) & TRN_HL, DELAY(-1,-1,40NS), + ANY_CH_AB & TRN_LH, DELAY(-1,-1,40NS), + ANY_CH_AB & TRN_HL, DELAY(-1,-1,35NS), + CHANGED(C0,0) & TRN_LH, DELAY(-1,-1,34NS), + DELAY(-1,-1,41NS) ;DEFAULT + ) + } + SUM2_O = { + CASE( + ANY_CH_AB & TRN_LH, DELAY(-1,-1,40NS), + CHANGED(C0,0) & TRN_HL, DELAY(-1,-1,42NS), + CHANGED(C0,0) & TRN_LH, DELAY(-1,-1,38NS), + ANY_CH_AB & TRN_HL, DELAY(-1,-1,35NS), + DELAY(-1,-1,43NS) ;DEFAULT + ) + } + C2_O = { + CASE( + ANY_CH_AB & TRN_LH, DELAY(-1,-1,40NS), + ANY_CH_AB & TRN_HL, DELAY(-1,-1,35NS), + CHANGED(C0,0) & TRN_HL, DELAY(-1,17NS,27NS), + CHANGED(C0,0) & TRN_LH, DELAY(-1,12NS,19NS), + DELAY(-1,18NS,41NS) ;DEFAULT + ) + } .ENDS *--------- *$ * 7483A 4-BIT BINARY FULL ADDERS WITH FAST CARRY * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/25/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES .SUBCKT 7483A C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I C4_O + SUM1_O SUM2_O SUM3_O SUM4_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 U83ALOG LOGICEXP(9,14) DPWR DGND + C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I + C0 A1 A2 A3 A4 B1 B2 B3 B4 C4 SUM1 SUM2 SUM3 SUM4 + D0_GATE IO_STD IO_LEVEL = {IO_LEVEL} + + LOGIC: + C0 = { C0_I } + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + B1 = { B1_I } + B2 = { B2_I } + B3 = { B3_I } + B4 = { B4_I } + + NAND4 = { ~(A4 & B4) } + NAND3 = { ~(A3 & B3) } + NAND2 = { ~(A2 & B2) } + NAND1 = { ~(A1 & B1) } + NOR4 = { ~(A4 | B4) } + NOR3 = { ~(A3 | B3) } + NOR2 = { ~(A2 | B2) } + NOR1 = { ~(A1 | B1) } + C0BAR = { ~C0 } + + SUM1 = { (NAND1 & ~NOR1) ^ C0 } + SUM2 = { (NAND2 & ~NOR2) ^ (~(NOR1 | (NAND1 & C0BAR))) } + SUM3 = { (NAND3 & ~NOR3) ^ (~(NOR2 | (NOR1 & NAND2) | + (NAND2 & NAND1 & C0BAR))) } + SUM4 = { (NAND4 & ~NOR4) ^ (~(NOR3 | (NOR2 & NAND3) | + (NOR1 & NAND3 & NAND2) | (NAND3 & NAND2 & NAND1 & C0BAR))) } + C4 = { ~( NOR4 | (NOR3 & NAND4) | (NOR2 & NAND4 & NAND3) | + (NOR1 & NAND4 & NAND3 & NAND2) | + (NAND4 & NAND3 & NAND2 & NAND1 & C0BAR) ) } U83ADLY PINDLY(5,0,9) DPWR DGND + SUM1 SUM2 SUM3 SUM4 C4 + C0 A1 A2 A3 A4 B1 B2 B3 B4 + SUM1_O SUM2_O SUM3_O SUM4_O C4_O + IO_STD MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_AB = { CHANGED(A1,0) | CHANGED(B1,0) | CHANGED(A2,0) | + CHANGED(B2,0) | CHANGED(A3,0) | CHANGED(B3,0) | + CHANGED(A4,0) | CHANGED(B4,0) } + + + PINDLY: + SUM1_O SUM2_O SUM3_O SUM4_O = { + CASE( + ANY_CH_AB, DELAY(-1,16NS,24NS), + CHANGED(C0,0) & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(C0,0) & TRN_HL, DELAY(-1,12NS,21NS), + DELAY(-1,17NS,25NS) ;DEFAULT + ) + } + C4_O = { + CASE( + CHANGED(C0,0) & TRN_HL, DELAY(-1,11NS,16NS), + ANY_CH_AB & TRN_HL, DELAY(-1,11NS,16NS), + (ANY_CH_AB | CHANGED(C0,0)) & TRN_LH, DELAY(-1,9NS,14NS), + DELAY(-1,12NS,17NS) ;DEFAULT + ) + } .ENDS *--------- *$ * 7485 4-BIT MAGNITUDE COMPARATOR * * NOTE : THE SPECS FOR 1,2,AND 3 GATE LEVELS PROP DELAYS ARE GIVEN; HOWEVER, * ONLY PROP DELAY FOR 3 GATE LEVELS IS USED IN THIS LIBRARY. * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-20-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES .SUBCKT 7485 A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + AGBIN_I AEBIN_I ALBIN_I AGBOUT_O AEBOUT_O ALBOUT_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U85LOG LOGICEXP(11,14) DPWR DGND + A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I AGBIN_I AEBIN_I ALBIN_I + A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN + AGBOUT AEBOUT ALBOUT + D0_GATE + IO_STD IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + A3 = { A3_I } + A2 = { A2_I } + A1 = { A1_I } + A0 = { A0_I } + B3 = { B3_I } + B2 = { B2_I } + B1 = { B1_I } + B0 = { B0_I } + AGBIN = { AGBIN_I } + AEBIN = { AEBIN_I } + ALBIN = { ALBIN_I } + * INTERMEDIATE TERMS: + C3 = { ~(A3 & B3) } + C2 = { ~(A2 & B2) } + C1 = { ~(A1 & B1) } + C0 = { ~(A0 & B0) } + A3C3 = { A3 & C3 } + A2C2 = { A2 & C2 } + A1C1 = { A1 & C1 } + A0C0 = { A0 & C0 } + B3C3 = { B3 & C3 } + B2C2 = { B2 & C2 } + B1C1 = { B1 & C1 } + B0C0 = { B0 & C0 } + D3 = { ~(A3C3 | B3C3) } + D2 = { ~(A2C2 | B2C2) } + D1 = { ~(A1C1 | B1C1) } + D0 = { ~(A0C0 | B0C0) } + D32 = { D3 & D2 } + D31 = { D32 & D1 } + D30 = { D31 & D0 } + * OUTPUT ASSIGNMENTS: + AGBOUT = { ~B3C3 & ~(B2C2 & D3) & ~(B1C1 & D32) & ~(B0C0 & D31) & + ~(ALBIN & D30) & ~(AEBIN & D30) } + AEBOUT = { D30 & AEBIN } + ALBOUT = { ~(AEBIN & D30) & ~(AGBIN & D30) & ~(A0C0 & D31) & + ~(A1C1 & D32) & ~(A2C2 & D3) & ~A3C3 } U85DLY PINDLY(3,0,11) DPWR DGND + AGBOUT AEBOUT ALBOUT + A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN + AGBOUT_O AEBOUT_O ALBOUT_O + IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATA_CHANGE = { CHANGED(A3,0) | CHANGED(A2,0) | CHANGED(A1,0) | CHANGED(A0,0) + | CHANGED(B3,0) | CHANGED(B2,0) | CHANGED(B1,0) | CHANGED(B0,0) } + AEBIN_CHANGE = { CHANGED(AEBIN,0) } + ABIN_CHANGE = { AEBIN_CHANGE | CHANGED(ALBIN,0) | CHANGED(AGBIN,0) } + + PINDLY: + AGBOUT_O ALBOUT_O = { ;AGBOUT & ALBOUT HAS THE SAME DELAY SO CAN BE GROUPPED + CASE( + DATA_CHANGE & TRN_LH, DELAY(-1,17NS,26NS), + DATA_CHANGE & TRN_HL, DELAY(-1,20NS,30NS), + ABIN_CHANGE & TRN_LH, DELAY(-1,7NS,11NS), + ABIN_CHANGE & TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,31NS) ;DEFAULT + ) + } + AEBOUT_O = { + CASE( + DATA_CHANGE & TRN_LH, DELAY(-1,23NS,35NS), + DATA_CHANGE & TRN_HL, DELAY(-1,20NS,30NS), + AEBIN_CHANGE & TRN_LH, DELAY(-1,13NS,20NS), + AEBIN_CHANGE & TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,24NS,36NS) ;DEFAULT + ) + } .ENDS *-------- *$ * 7486 Quadruple 2-input Exclusive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names .subckt 7486 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_86_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_86_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_86_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_86_1 ugate ( + tplhty=9ns tplhmx=17ns + tphlty=5ns tphlmx=11ns + ) .model D_86_2 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=7ns tphlmx=16ns + ) .model D_86_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) *--------- *$ * 7490A COUNTER DECADE 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-2-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 7490A R91_I R92_I CKA_I CKB_I R01_I R02_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 JKFF(1) DPWR DGND + SET9BAR CLRBAR CKA $D_HI $D_HI QA $D_NC + D0_EFF IO_STD U2 JKFF(1) DPWR DGND + $D_HI CLRBAR23 CKB QDBAR $D_HI QB $D_NC + D0_EFF IO_STD U3 JKFF(1) DPWR DGND + $D_HI CLRBAR23 QB $D_HI $D_HI QC $D_NC + D0_EFF IO_STD U4 JKFF(1) DPWR DGND + SET9BAR CLRBAR CKB J4 QD QD QDBAR + D0_EFF IO_STD U90ALOG LOGICEXP (8,10) DPWR DGND + R91_I R92_I CKA_I CKB_I R01_I R02_I QB QC + R91 R92 CKA CKB R01 R02 J4 SET9BAR CLRBAR CLRBAR23 + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + R91 = { R91_I } + R92 = { R92_I } + CKA = { CKA_I } + CKB = { CKB_I } + R01 = { R01_I } + R02 = { R02_I } + SET9BAR = { ~(R91 & R92) } + CLRBAR = { ~(R01 & R02) } + CLRBAR23 = { CLRBAR & SET9BAR } + J4 = { QB & QC } U90ADLY PINDLY (4,0,4) DPWR DGND + QA QB QC QD + CKA CKB CLRBAR SET9BAR + QA_O QB_O QC_O QD_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKEDA = { CHANGED_HL(CKA,0) } + CLOCKEDB = { CHANGED_HL(CKB,0) } + SETNINE = { CHANGED_HL(SET9BAR,0) } + + PINDLY: + QA_O = { + CASE ( + CLOCKEDA & TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDA & TRN_HL, DELAY(-1,12NS,18NS), + SETNINE, DELAY(-1,20NS,30NS), + DELAY(-1,26NS,40NS) + ) + } + QB_O = { + CASE ( + CLOCKEDB & TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDB & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,26NS,40NS) + ) + } + QC_O = { + CASE ( + CLOCKEDB & TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } + QD_O = { + CASE ( + SETNINE, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } U90ACON CONSTRAINT (8) DPWR DGND + CKA CKB CLRBAR SET9BAR R01 R02 R91 R92 + IO_STD + + FREQ: + NODE = CKA + MAXFREQ = 32MEGHZ + FREQ: + NODE = CKB + MAXFREQ = 16MEGHZ + WIDTH: + NODE = CKA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CKB + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = R01 + MIN_LO = 15NS + WHEN = { SET9BAR!='0 } + WIDTH: + NODE = R02 + MIN_LO = 15NS + WHEN = { SET9BAR!='0 } + WIDTH: + NODE = R91 + MIN_LO = 15NS + WIDTH: + NODE = R92 + MIN_LO = 15NS + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKA + RELEASETIME_LH = 25NS + WHEN = { SET9BAR!='0 & CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKB + RELEASETIME_LH = 25NS + WHEN = { SET9BAR!='0 & CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R91 R92 + CLOCK HL = CKA + RELEASETIME_LH = 25NS + WHEN = { CHANGED(SET9BAR,25NS) } + SETUP_HOLD: + DATA(2) = R91 R92 + CLOCK HL = CKB + RELEASETIME_LH = 25NS + WHEN = { CHANGED(SET9BAR,25NS) } .ENDS *--------- *$ * 7491A 8-BIT SHIFT REGISTERS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTKKY DATA BOOK, 1988, TI * NH 7/13/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES .SUBCKT 7491A CLK_I A_I B_I QH_O QHBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 BUFA(3) DPWR DGND CLK_I A_I B_I CLK A B + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 NAND(2) DPWR DGND A B KA + D0_GATE IO_STD U3 INVA(2) DPWR DGND CLK KA CLKBAR JA + D0_GATE IO_STD U5 JKFF(8) DPWR DGND $D_HI $D_HI CLKBAR + JA QA QB QC QD QE QF QG KA QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR + QA QB QC QD QE QF QG QH QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR QHBAR + D0_EFF IO_STD U91DLY PINDLY(2,0,1) DPWR DGND + QH QHBAR + CLK + QH_O QHBAR_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QH_O QHBAR_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,24NS,40NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,27NS,40NS), + DELAY(-1,28NS,41NS) ;DEFAULT + ) + } U91CON CONSTRAINT(3) DPWR DGND + CLK A B + IO_STD + + FREQ: + NODE = CLK + MAXFREQ = 10MEG + + WIDTH: + NODE = CLK + MIN_HI = 25NS + MIN_LO = 25NS + + SETUP_HOLD: + DATA(2) A B + CLOCK LH = CLK + SETUPTIME = 25NS .ENDS *--------- *$ * 7492A COUNTER DIVIDE-BY-12 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-3-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE -- THE CKA TO QD PIN DELAY IS NOT INCLUDED IN THIS MODEL SINCE * THE DIV2 AND DIV8 SECTIONS OF THE COUNTER ACT INDEPENDENTLY. .SUBCKT 7492A CKA_I CKB_I R01_I R02_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 JKFF(1) DPWR DGND + $D_HI CLRBAR CKA $D_HI $D_HI QA $D_NC + D0_EFF IO_STD U2 JKFF(1) DPWR DGND + $D_HI CLRBAR CKB QCBAR $D_HI QB $D_NC + D0_EFF IO_STD U3 JKFF(1) DPWR DGND + $D_HI CLRBAR CKB QB $D_HI QC QCBAR + D0_EFF IO_STD U4 JKFF(1) DPWR DGND + $D_HI CLRBAR QC $D_HI $D_HI QD $D_NC + D0_EFF IO_STD U5 BUFA(4) DPWR DGND + CKA_I CKB_I R01_I R02_I CKA CKB R01 R02 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U6 NAND(2) DPWR DGND + R01 R02 CLRBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U92ADLY PINDLY (4,0,3) DPWR DGND + QA QB QC QD + CKA CKB CLRBAR + QA_O QB_O QC_O QD_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKEDA = { CHANGED_HL(CKA,0) } + CLOCKEDB = { CHANGED_HL(CKB,0) } + CLEARED = { CHANGED_HL(CLRBAR,0) } + + PINDLY: + QA_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDA & TRN_HL, DELAY(-1,12NS,18NS), + DELAY(-1,26NS,40NS) + ) + } + QB_O QC_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDB & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,26NS,40NS) + ) + } + QD_O = { + CASE ( + TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } U92ACON CONSTRAINT (5) DPWR DGND + CKA CKB CLRBAR R01 R02 + IO_STD + + FREQ: + NODE = CKA + MAXFREQ = 32MEGHZ + FREQ: + NODE = CKB + MAXFREQ = 16MEGHZ + WIDTH: + NODE = CKA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CKB + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = R01 + MIN_HI = 15NS + WIDTH: + NODE = R02 + MIN_HI = 15NS + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKA + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKB + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } .ENDS *--------- *$ * 7493A COUNTER BINARY 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 6-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE -- THE CKA TO QD PIN DELAY IS NOT INCLUDED IN THIS MODEL SINCE * THE DIV2 AND DIV8 SECTIONS OF THE COUNTER ACT INDEPENDENTLY. .SUBCKT 7493A CKA_I CKB_I R01_I R02_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 JKFF(1) DPWR DGND + $D_HI CLRBAR CKA $D_HI $D_HI QA $D_NC + D0_EFF IO_STD U2 JKFF(1) DPWR DGND + $D_HI CLRBAR CKB $D_HI $D_HI QB $D_NC + D0_EFF IO_STD U3 JKFF(1) DPWR DGND + $D_HI CLRBAR QB $D_HI $D_HI QC $D_NC + D0_EFF IO_STD U4 JKFF(1) DPWR DGND + $D_HI CLRBAR QC $D_HI $D_HI QD $D_NC + D0_EFF IO_STD U5 BUFA(4) DPWR DGND + CKA_I CKB_I R01_I R02_I CKA CKB R01 R02 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U6 NAND(2) DPWR DGND + R01 R02 CLRBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U93ADLY PINDLY (4,0,3) DPWR DGND + QA QB QC QD + CKA CKB CLRBAR + QA_O QB_O QC_O QD_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKEDA = { CHANGED_HL(CKA,0) } + CLOCKEDB = { CHANGED_HL(CKB,0) } + CLEARED = { CHANGED_HL(CLRBAR,0) } + + PINDLY: + QA_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDA & TRN_HL, DELAY(-1,12NS,18NS), + DELAY(-1,26NS,40NS) + ) + } + QB_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDB & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,26NS,40NS) + ) + } + QC_O = { + CASE ( + TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } + QD_O = { + CASE ( + CLEARED, DELAY(-1,26NS,40NS), + DELAY(-1,34NS,51NS) + ) + } U93ACON CONSTRAINT (5) DPWR DGND + CKA CKB CLRBAR R01 R02 + IO_STD + + FREQ: + NODE = CKA + MAXFREQ = 32MEGHZ + FREQ: + NODE = CKB + MAXFREQ = 16MEGHZ + WIDTH: + NODE = CKA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CKB + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = R01 + MIN_HI = 15NS + WIDTH: + NODE = R02 + MIN_HI = 15NS + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKA + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKB + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } .ENDS *--------- *$ * 7494 4-BIT SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1988, TI * NH 7/1/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES .SUBCKT 7494 CLR_I CLK_I SER_I PE1_I P1A_I P1B_I P1C_I P1D_I + PE2_I P2A_I P2B_I P2C_I P2D_I QD_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 U94LOG LOGICEXP(13,20) DPWR DGND + CLR_I CLK_I SER_I PE1_I P1A_I P1B_I P1C_I P1D_I PE2_I P2A_I P2B_I P2C_I P2D_I + CLR CLK SER PE1 P1A P1B P1C P1D PE2 P2A P2B P2C P2D SERBAR CLKBAR CLRBAR + PRESETA PRESETB PRESETC PRESETD + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} + + LOGIC: * * OUTPUT ASSIGNMENT * + CLR = { CLR_I } + CLK = { CLK_I } + SER = { SER_I } + PE1 = { PE1_I } + P1A = { P1A_I } + P1B = { P1B_I } + P1C = { P1C_I } + P1D = { P1D_I } + PE2 = { PE2_I } + P2A = { P2A_I } + P2B = { P2B_I } + P2C = { P2C_I } + P2D = { P2D_I } * + PRESETA = { ~( (PE1 & P1A) | (PE2 & P2A) ) } + PRESETB = { ~( (PE1 & P1B) | (PE2 & P2B) ) } + PRESETC = { ~( (PE1 & P1C) | (PE2 & P2C) ) } + PRESETD = { ~( (PE1 & P1D) | (PE2 & P2D) ) } + SERBAR = { ~SER } + CLKBAR = { ~CLK } + CLRBAR = { ~CLR } U1 JKFF(1) DPWR DGND PRESETA CLRBAR CLKBAR SER SERBAR QA QABAR + D0_EFF IO_STD U2 JKFF(1) DPWR DGND PRESETB CLRBAR CLKBAR QA QABAR QB QBBAR + D0_EFF IO_STD U3 JKFF(1) DPWR DGND PRESETC CLRBAR CLKBAR QB QBBAR QC QCBAR + D0_EFF IO_STD U4 JKFF(1) DPWR DGND PRESETD CLRBAR CLKBAR QC QCBAR LQD QDBAR + D0_EFF IO_STD U94DLY PINDLY(1,0,6) DPWR DGND + LQD + CLK CLR PE1 P1D PE2 P2D + QD_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + PRESET = { (PE1!='0 & P1D!='0) | (PE2!='0 & P2D!='0) } + + PINDLY: + QD_O = { + CASE( + PRESET, DELAY(-1,-1,35NS), + CHANGED_LH(CLR,0) & TRN_HL, DELAY(-1,-1,40NS), + CHANGED_LH(CLK,0), DELAY(-1,25NS,40NS), + DELAY(11NS,26NS,41NS) ;DEFAULT + ) + } U94CON CONSTRAINT(17) DPWR DGND + CLK CLR SER PE1 PE2 P1A P1B P1C P1D P2A P2B P2C P2D PRESETA PRESETB PRESETC + PRESETD + IO_STD + + BOOLEAN: + PE1_EN = { PE1!='0 } + PE2_EN = { PE2!='0 } + + FREQ: + NODE = CLK + MAXFREQ = 10MEG + + WIDTH: + NODE = CLK + MIN_HI = 35NS + MIN_LO = 35NS + + WIDTH: + NODE = CLR + MIN_HI = 30NS + + WIDTH: + NODE = P1A + MIN_HI = 30NS + WHEN = { PE1_EN } + + WIDTH: + NODE = P2A + MIN_HI = 30NS + WHEN = { PE2_EN } + + WIDTH: + NODE = P1B + MIN_HI = 30NS + WHEN = { PE1_EN } + + WIDTH: + NODE = P2B + MIN_HI = 30NS + WHEN = { PE2_EN } + + WIDTH: + NODE = P1C + MIN_HI = 30NS + WHEN = { PE1_EN } + + WIDTH: + NODE = P2C + MIN_HI = 30NS + WHEN = { PE2_EN } + + WIDTH: + NODE = P1D + MIN_HI = 30NS + WHEN = { PE1_EN } + + WIDTH: + NODE = P2D + MIN_HI = 30NS + WHEN = { PE2_EN } + + SETUP_HOLD: + DATA(1) SER + CLOCK LH = CLK + SETUPTIME_HI = 35NS + SETUPTIME_LO = 25NS + WHEN = { CLR!='1 & PRESETA!='0 & PRESETB!='0 & PRESETC!='0 & PRESETD!='0 } .ENDS *--------- *$ * 7495A 4-BIT PARALLEL SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-29-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES .SUBCKT 7495A MODE_I CLK1_I CLK2_I SER_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U95ALOG LOGICEXP(11,17) DPWR DGND + MODE_I CLK1_I CLK2_I SER_I A_I B_I C_I D_I QA QB QC + MODE CLK1 CLK2 SER A B C D CLK JA JB JC JD KA KB KC KD + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + LOGIC: + MODE = { MODE_I } + CLK1 = { CLK1_I } + CLK2 = { CLK2_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERM + MODEBAR = { ~MODE } + + CLK = { ((MODEBAR & CLK1) | (MODE & CLK2)) } + JA = { (MODEBAR & SER) | (MODE & A) } + JB = { (MODEBAR & QA) | (MODE & B) } + JC = { (MODEBAR & QB) | (MODE & C) } + JD = { (MODEBAR & QC) | (MODE & D) } + KA = { ~JA } + KB = { ~JB } + KC = { ~JC } + KD = { ~JD } U1 JKFF(4) DPWR DGND $D_HI $D_HI CLK + JA JB JC JD KA KB KC KD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_STD U95ADLY PINDLY(4,0,2) DPWR DGND + QA QB QC QD + CLK1 CLK2 + QA_O QB_O QC_O QD_O + IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLK = { CHANGED_HL(CLK1,0) | CHANGED_HL(CLK2,0) } + + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLK & TRN_LH, DELAY(-1,18NS,27NS), + CLK & TRN_HL, DELAY(-1,21NS,32NS), + DELAY(-1,22NS,33NS) ;DEFAULT + ) + } U95ACON CONSTRAINT(8) DPWR DGND + MODE CLK1 CLK2 SER A B C D + IO_STD + + FREQ: + NODE = CLK1 + MAXFREQ = 25MEG + + FREQ: + NODE = CLK2 + MAXFREQ = 25MEG + + WIDTH: + NODE = CLK1 + MIN_HI = 20NS + + WIDTH: + NODE = CLK2 + MIN_HI = 20NS + + SETUP_HOLD: + DATA(4) A B C D + CLOCK HL = CLK2 + SETUPTIME = 15NS + WHEN = { MODE != '0 } + + SETUP_HOLD: + DATA(1) SER + CLOCK HL = CLK1 + SETUPTIME = 15NS + WHEN = { MODE != '1 } + + SETUP_HOLD: ; T_ENABLE1 + DATA(1) MODE + CLOCK HL = CLK1 + SETUPTIME_LO = 15NS + MESSAGE = "TENABLE1 IS NOT MET" + + SETUP_HOLD: ; T_ENABLE2 + DATA(1) MODE + CLOCK HL = CLK2 + SETUPTIME_HI = 15NS + MESSAGE = "TENABLE2 IS NOT MET" + + SETUP_HOLD: ; T_INHIBIT1 + DATA(1) MODE + CLOCK LH = CLK1 + SETUPTIME_HI = 5NS + MESSAGE = "TINHIBIT1 IS NOT MET" + + SETUP_HOLD: ; T_INHIBIT2 + DATA(1) MODE + CLOCK LH = CLK2 + SETUPTIME_LO = 5NS + MESSAGE = "TINHIBIT2 IS NOT MET" .ENDS *-------- *$ * 7496 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-1-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES .SUBCKT 7496 CLRBAR_I CLK_I SER_I PRE_I A_I B_I C_I D_I E_I + QA_O QB_O QC_O QD_O QE_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 BUFA(9) DPWR DGND + CLRBAR_I CLK_I SER_I PRE_I A_I B_I C_I D_I E_I + CLRBAR CLK SER PRE A B C D E + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 NANDA(2,5) DPWR DGND + PRE A PRE B PRE C PRE D PRE E + OUT_A OUT_B OUT_C OUT_D OUT_E + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 DFF(1) DPWR DGND + OUT_A CLRBAR CLK + SER + QA + $D_NC + D0_EFF IO_STD U4 DFF(1) DPWR DGND + OUT_B CLRBAR CLK + QA + QB + $D_NC + D0_EFF IO_STD U5 DFF(1) DPWR DGND + OUT_C CLRBAR CLK + QB + QC + $D_NC + D0_EFF IO_STD U6 DFF(1) DPWR DGND + OUT_D CLRBAR CLK + QC + QD + $D_NC + D0_EFF IO_STD U7 DFF(1) DPWR DGND + OUT_E CLRBAR CLK + QD + QE + $D_NC + D0_EFF IO_STD USTD96DLY PINDLY(5,0,3) DPWR DGND + QA QB QC QD QE + CLRBAR PRE CLK + QA_O QB_O QC_O QD_O QE_O + IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O QE_O = { + CASE( + CHANGED_LH(PRE,0), DELAY(-1,28NS,35NS), + CHANGED_LH(CLK,0), DELAY(-1,25NS,40NS), + CHANGED_HL(CLRBAR,0), DELAY(-1,-1,55NS), + DELAY(-1,-1,56NS) ;DEFAULT + ) + } USTD96CON CONSTRAINT(4) DPWR DGND + CLRBAR CLK SER PRE + IO_STD + + FREQ: + NODE = CLK + MAXFREQ = 10MEG + + WIDTH: + NODE = CLK + MIN_HI = 35NS + MIN_LO = 35NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 30NS + + WIDTH: + NODE = PRE + MIN_HI = 30NS + + SETUP_HOLD: + DATA(1) = SER ; NOR SETTING + CLOCK LH = CLK ; CHECK SERIAL INPUT SETUPTIME WHEN NOT CLEARING + SETUPTIME = 30NS + WHEN = { (CLRBAR != '0) & (PRE != '1) } .ENDS *--------- *$ * 74100 8-Bit Bistable Latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/17/89 Update interface and model names .subckt 74100 1C 1D1 1D2 1D3 1D4 1Q1 1Q2 1Q3 1Q4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * There are 2 4-bit latches in the real 74100 IC. However, the model here is * designed with only 1 4-bit latch. In case of 8-bit latches needed, please use * the SUBCKT twice. U1 dltch(4) DPWR DGND + $D_HI $D_HI 1C + 1D1 1D2 1D3 1D4 + 1Q1 1Q2 1Q3 1Q4 $D_NC $D_NC $D_NC $D_NC + D_100 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_100 ugff ( + twghmn=20ns tsudgmn=20ns + thdgmn=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=16ns + tpdqlhmx=30ns tpdqhlty=14ns + tpdqhlmx=25ns + ) *-------- *$ * 74107 Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names * jgt 04/20/95 Changed to use jkff's * .subckt 74107 CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + CLRBAR J K CLRBAR_BUF J_BUF K_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2BUF buf DPWR DGND + CLK CLK_BUF + D_107_4 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 JKff(1) DPWR DGND + $D_HI CLRBAR_BUF CLKBAR W1 W2 Y YB + D_107_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 JKff(1) DPWR DGND + $D_HI CLRBAR_BUF CLK_BUF Y YB QBUF QBAR_BUF + D_107_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(3) DPWR DGND + CLK_BUF J_BUF K_BUF CLKBAR JB KB + D0_GATE IO_STD U4 ao(3,2) DPWR DGND + J_BUF K_BUF QBAR_BUFD J_BUF KB $D_HI W1 + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} U5 ao(3,2) DPWR DGND + J_BUF K_BUF QBUFD JB K_BUF $D_HI W2 + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} UBUF bufa(4) DPWR DGND + QBUF QBAR_BUF QBUF QBAR_BUF Q QBAR QBUFD QBAR_BUFD + D_107_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_107_1 ueff ( + tppcqlhty=10ns tppcqlhmx=15ns + tppcqhlty=10ns tppcqhlmx=15ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=18ns tpclkqhlmx=28ns + twclkhmx=20ns twclklmx=20ns + twclkhty=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=10ns tsudclkty=20ns + thdclkmx=6ns thdclkty=6ns + ) .model D_107_2 ueff ( + tppcqlhty=10ns tppcqlhmx=19ns + tppcqhlty=19ns tppcqhlmx=34ns + tpclkqlhty=10ns tpclkqlhmx=19ns + tpclkqhlty=19ns tpclkqhlmx=34ns + twclkhmx=20ns twclklmx=20ns + twclkhty=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=10ns tsudclkty=20ns + thdclkmx=6ns thdclkty=6ns + ) .model D_107_3 ugate ( + tplhty=6ns tplhmx=6ns + tphlty=6ns tphlmx=6ns + ) .model D_107_4 ugate ( + tplhmn=6ns tplhmx=6ns + ) *--------- *$ * 74109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/30/89 Update interface and model names .subckt 74109 CLK PREBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + PREBAR CLRBAR J PREBAR_BUF CLRBAR_BUF J_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J_BUF K $D_NC QBAR + D_109_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J_BUF K Q $D_NC + D_109_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 inva(2) DPWR DGND + CLK KBAR CLKBAR K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} .ends .model D_109_1 ueff ( + tppcqlhty=10ns tppcqlhmx=15ns + tppcqhlty=10ns tppcqhlmx=15ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=18ns tpclkqhlmx=28ns + twclkhmx=20ns twclklmx=20ns + twclkhty=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=10ns tsudclkty=20ns + thdclkmx=6ns thdclkty=6ns + ) .model D_109_2 ueff ( + tppcqlhty=23ns tppcqlhmx=35ns + tppcqhlty=17ns tppcqhlmx=25ns + tpclkqlhty=10ns tpclkqlhmx=16ns + tpclkqhlty=18ns tpclkqhlmx=28ns + twclkhmx=20ns twclklmx=20ns + twclkhty=20ns twclklty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=10ns tsudclkty=20ns + thdclkmx=6ns thdclkty=6ns + ) *--------- *$ * 74110 And-Gated J-K Master-Slave Flip-Flops with Data Lockout * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/18/89 Update interface and model names .subckt 74110 CLK PREBAR CLRBAR J1 J2 J3 K1 K2 K3 Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + PREBAR CLRBAR PREBAR_BUF CLRBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 inv DPWR DGND + CLK CLKBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U2 anda(3,2) DPWR DGND + J1 J2 J3 K1 K2 K3 J K + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J K QI $D_NC + D_110_1 IO_STD MNTYMXDLY={MNTYMXDLY} U4 dff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR QI Q QBAR + D_110_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_110_1 ueff ( + tsudclkmn=20ns thdclkmn=5ns + twclkhmn=25ns twclklmn=25ns + twpclmn=25ns + ) .model D_110_2 ueff ( + tppcqlhty=12ns tppcqlhmx=20ns + tsudclkmn=20ns thdclkmn=5ns + tppcqhlty=18ns tppcqhlmx=25ns + tpclkqlhty=20ns tpclkqlhmx=30ns + tpclkqhlty=13ns tpclkqhlmx=20ns + twclkhmn=25ns twpclmn=25ns + ) *-------- *$ * 74111 Dual J-K Master-Slave Flip-Flops with Data Lockout * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/30/89 Update interface and model names .subckt 74111 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + PREBAR CLRBAR PREBAR_BUF CLRBAR_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UA inv DPWR DGND + CLK CLKBAR + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J K QI $D_NC + D_111_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 dltch(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLK QI Q QBAR + D_111_2 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_111_1 ueff ( + thdclkty=30ns thdclkmx=30ns + twclkhty=25ns twclkhmx=25ns + twclklty=25ns twclklmx=25ns + twpclty=25ns twpclmx=25ns + ) .model D_111_2 ugff ( + tppcqlhty=12ns tppcqlhmx=18ns + tppcqhlty=21ns tppcqhlmx=30ns + tpgqlhty=12ns tpgqlhmx=17ns + tpgqhlty=20ns tpgqhlmx=30ns + twghmx=25ns twghty=25ns + twpclmx=25ns twpclty=25ns + ) *-------- *$ * 74121 Non-retriggerable Monostable Multivibrator w/Schmitt-Trigger Inputs * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * rbh 06/02/92 Added dummy R/C pins * * Notes: * 1. The RINT, CEXT, and REXT/CEXT pins are not functional. The output * pulse width, tw(out), is controlled with the PULSE subcircuit * parameter. Note that this means that the pulse width is FIXED for * the duration of the simulation. You can specify this value in the * subcircuit call, e.g. X1 ... 74121 PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (50ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. .subckt 74121 A1 A2 B RINT CEXT REXT/CEXT Q Qbar + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=30ns IO_LEVEL=0 MNTYMXDLY=0 * R1 RINT 0 100MEG R2 RINT 0 100MEG R3 CEXT 0 100MEG R4 CEXT 0 100MEG R5 REXT/CEXT 0 100MEG R6 REXT/CEXT 0 100MEG * UA nand(2) DPWR DGND + A1 A2 A + D0_GATE IO_STD_ST IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + A A_dly + D_121_A_dly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigger nand(2) DPWR DGND + A_dly B Trigger + D0_GATE IO_STD_ST IO_LEVEL={IO_LEVEL} UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0S 0 + 1NS Z * UOutputs jkff(1) DPWR DGND + $D_HI Clear Trigger $D_HI $D_LO Q_ Q_Bar + D_121_Outputs IO_STD MNTYMXDLY={MNTYMXDLY} * UQ_Buf buf DPWR DGND + Q_ Q_Buf + D0_GATE IO_STD UQx isx(1) DPWR DGND + q_ q_x + D0_GATE IO_STD UQ0 is0(1) DPWR DGND + q_ q_0 + D0_GATE IO_STD UQ0_Bar inv DPWR DGND + q_0 q0_bar + D0_GATE IO_STD UQ_Rise or(2) DPWR DGND + Q_Buf q_x q_rise + D0_GATE IO_STD UTrigdly dlyline DPWR DGND + Trigger trigdly + D_121_trigdly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_STD UTrigx_bar inv DPWR DGND + trigx trigx_fall + D0_GATE IO_STD UReset0 nand(2) DPWR DGND + q_rise trigx_fall reset0 + D0_GATE IO_STD UClear jkff(1) dpwr dgnd + q0_bar $d_hi reset0 $d_lo $d_hi Clear $d_nc + D_121_pulse IO_STD MNTYMXDLY={MNTYMXDLY} * * Output buffers * UQ inv DPWR DGND + q_bar Q + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UQBar buf DPWR DGND + q_bar QBAR + D_121_Qbar IO_STD IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_121_pulse ueff( + tpclkqhlmn={pulse} tpclkqhlty={pulse} tpclkqhlmx={pulse} + ) .ends 74121 .model D_121_Outputs ueff ( + twclklty=35ns twclklmx=55ns + tpclkqlhty=35ns tpclkqlhmx=55ns + tpclkqhlty=35ns tpclkqhlmx=55ns + ) .model D_121_A_dly udly ( + dlyty=10ns dlymx=15ns + ) .model D_121_trigdly udly ( + dlyty=35ns dlymx=55ns + ) .model D_121_Qbar ugate ( + tplhty=5ns tplhmx=10ns + tphlty=5ns tphlmx=10ns + ) *-------- *$ * 74122 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * rbh 06/02/92 Added dummy R/C pins * * Notes: * 1. The RINT, CEXT, and REXT/CEXT pins are not functional. The output * pulse width, tw(out), is controlled with the PULSE subcircuit * parameter. Note that this means that the pulse width is FIXED for * the duration of the simulation. You can specify this value in the * subcircuit call, e.g. X1 ... 74122 PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (40ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 74122 CLRBAR A1 A2 B1 B2 RINT CEXT REXT/CEXT Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=45ns IO_LEVEL=0 MNTYMXDLY=0 * R1 RINT 0 100MEG R2 RINT 0 100MEG R3 CEXT 0 100MEG R4 CEXT 0 100MEG R5 REXT/CEXT 0 100MEG R6 REXT/CEXT 0 100MEG * UA nand(2) DPWR DGND + A1 A2 A + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + A A_dly + D_122_A_dly IO_STD MNTYMXDLY={MNTYMXDLY} * UTrigger and(3) DPWR DGND + A_dly B1 B2 Trigger + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_STD UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_122_Outputs IO_STD IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_122_trigdly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_STD UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_STD UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_122_tedge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_STD UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_STD UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_STD UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_122_edge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_STD UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset $d_nc + D_122_pulse IO_STD MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_122_pulse ueff( + tpclkqhlmn={pulse-1ns+1ns} + tpclkqhlty={pulse-1ns+1ns} ;-1 for trigdly, +1=tp(trig)-tp(reset) + tpclkqhlmx={pulse-1ns+1ns} + ) .ends 74122 .model D_122_A_dly udly ( + dlyty=3ns dlymx=5ns + ) .model D_122_Outputs ueff ( + twclklty=19ns twclklmx=28ns + tpclkqlhty=19ns tpclkqlhmx=28ns + tpclkqhlty=27ns tpclkqhlmx=36ns + tppcqhlty=18ns tppcqhlmx=27ns + tppcqlhty=26ns tppcqlhmx=35ns + ) .model D_122_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_122_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_122_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *-------- *$ * 74123 Retriggerable Monostable Multivibrator * * The TTL Data Book, Vol 2, 1985, TI * rbh 06/14/91 Created * rbh 06/02/92 Added dummy R/C pins * * Notes: * 1. The CEXT and REXT/CEXT pins are not functional. The output * pulse width, tw(out), is controlled with the PULSE subcircuit * parameter. Note that this means that the pulse width is FIXED for * the duration of the simulation. You can specify this value in the * subcircuit call, e.g. X1 ... 74123 PARAMS: PULSE=1us * 2. Instead of a fixed minimum input pulse width (40ns), this model requires * the input pulse to be at least as long as the propagation delay through * the device. Input pulses which are shorter than this value produce * an X which is tw(out) in duration. * 3. Some prop delays are off by a few nanoseconds. .subckt 74123 CLRBAR A B CEXT REXT/CEXT Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: PULSE=45ns IO_LEVEL=0 MNTYMXDLY=0 * R1 CEXT 0 100MEG R2 CEXT 0 100MEG R3 REXT/CEXT 0 100MEG R4 REXT/CEXT 0 100MEG * UABar inv DPWR DGND + A ABar + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UAdly dlyline DPWR DGND + ABar A_dly + D_123_A_dly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigger and(2) DPWR DGND + A_dly B Trigger + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} * UTrigBar inv DPWR DGND + Trigger Trig_Bar + D0_GATE IO_STD UStart stim(1,1) DPWR DGND + Clear + IO_STM + 0ns 0 + 1ns Z UClear and(2) DPWR DGND + CLRBAR Reset Clear + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} UOutputs jkff(1) DPWR DGND + $D_HI Clear Trig_Bar $D_HI $D_LO Q QBAR + D_123_Outputs IO_STD IO_LEVEL={IO_LEVEL} MNTYMXDLY={MNTYMXDLY} * UTrigdly dlyline DPWR DGND + Trigger trigdly + D_123_trigdly IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx isx(1) DPWR DGND + trigdly trigx + D0_GATE IO_STD UTrigx_bar inv DPWR DGND + trigx trigx_bar + D0_GATE IO_STD UTrigx_barbar inv DPWR DGND + trigx_bar trigx_barbar + D_123_tedge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigx_fall and(2) DPWR DGND + trigx_barbar trigx_bar trigx_fall + D0_GATE IO_STD UReset0 nor(2) DPWR DGND + trigdly trigx_fall reset0 + D0_GATE IO_STD UTrig0 is0(1) DPWR DGND + Trigger Trig_0 + D0_GATE IO_STD UTrig0_Bar inv DPWR DGND + Trig_0 Trig0_Bar + D_123_edge IO_STD MNTYMXDLY={MNTYMXDLY} UTrigPreset or(2) DPWR DGND + Trig_0 Trig0_Bar TrigPreset + D0_GATE IO_STD UReset jkff(1) DPWR DGND + TrigPreset $d_hi reset0 $d_lo $d_hi reset $d_nc + D_123_pulse IO_STD MNTYMXDLY={MNTYMXDLY} * * Local timing model * .model D_123_pulse ueff( + tpclkqhlmn={pulse-1ns+1ns} + tpclkqhlty={pulse-1ns+1ns} ;-1 for trigdly, +1=tp(trig)-tp(reset) + tpclkqhlmx={pulse-1ns+1ns} + ) + ) .ends 74123 .model D_123_A_dly udly ( + dlyty=3ns dlymx=5ns + ) .model D_123_Outputs ueff ( + twclklty=19ns twclklmx=28ns + tpclkqlhty=19ns tpclkqlhmx=28ns + tpclkqhlty=27ns tpclkqhlmx=36ns + tppcqhlty=18ns tppcqhlmx=27ns + tppcqlhty=26ns tppcqlhmx=35ns + ) .model D_123_trigdly udly ( + dlymn=1ns dlyty=1ns dlymx=1ns + ) .model D_123_edge ugate( + tplhmn=1ns tplhty=1ns tplhmx=1ns + ) .model D_123_tedge ugate( + tphlmn=1ns tphlty=1ns tphlmx=1ns + ) *--------- *$ * 74125 Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74125 A GBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_125 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + GBAR G + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} .ends .model D_125 utgate ( + tplhty=8ns tplhmx=13ns + tphlty=12ns tphlmx=18ns + tpzhty=11ns tpzhmx=17ns + tpzlty=16ns tpzlmx=25ns + tphzty=5ns tphzmx=8ns + tplzty=7ns tplzmx=12ns + ) *--------- *$ * 74126 Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74126 A G Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_126 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_126 utgate ( + tplhty=8ns tplhmx=13ns + tphlty=12ns tphlmx=18ns + tpzhty=11ns tpzhmx=18ns + tpzlty=16ns tpzlmx=25ns + tphzty=10ns tphzmx=16ns + tplzty=12ns tplzmx=18ns + ) *--------- *$ * 74128 Line Drivers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74128 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_128 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_128 ugate ( + tplhty=6ns tplhmx=9ns + tphlty=8ns tphlmx=12ns + ) *-------- *$ * 74132 Quadruple 2-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74132 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled by the AtoD interface. U1 nand(2) DPWR DGND + A B Y + D_132 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends .model D_132 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *--------- *$ * 74136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names .subckt 74136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_136_1 IO_STD MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_136_2 IO_STD MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_136_3 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74136 .model D_136_1 ugate ( + tplhty=12ns tplhmx=18ns + ) .model D_136_2 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=3ns tphlmx=5ns + ) .model D_136_3 ugate ( + tphlty=39ns tphlmx=50ns + ) *--------- *$ * 74145 DECODER/DRIVER BCD-DECIMAL WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74145 A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U145LOG LOGICEXP (4,10) DPWR DGND + A_I B_I C_I D_I + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + DBAR = { ~D } + Y0 = { ~(DBAR & CBAR & BBAR & ABAR ) } + Y1 = { ~(DBAR & CBAR & BBAR & A ) } + Y2 = { ~(DBAR & CBAR & B & ABAR ) } + Y3 = { ~(DBAR & CBAR & B & A ) } + Y4 = { ~(DBAR & C & BBAR & ABAR ) } + Y5 = { ~(DBAR & C & BBAR & A ) } + Y6 = { ~(DBAR & C & B & ABAR ) } + Y7 = { ~(DBAR & C & B & A ) } + Y8 = { ~(D & CBAR & BBAR & ABAR ) } + Y9 = { ~(D & CBAR & BBAR & A ) } U145DLY PINDLY (10,0,0) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + IO_STD_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O = + { DELAY(-1,-1,50NS) } .ENDS *--------- *$ * 74147 PRIORITY ENCODER 10-4 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-31-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74147 IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I IN8_I IN9_I + A_O B_O C_O D_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U147LOG LOGICEXP (9,13) DPWR DGND + IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I IN8_I IN9_I + IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 + A B C D + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + IN1 = { IN1_I } + IN2 = { IN2_I } + IN3 = { IN3_I } + IN4 = { IN4_I } + IN5 = { IN5_I } + IN6 = { IN6_I } + IN7 = { IN7_I } + IN8 = { IN8_I } + IN9 = { IN9_I } + IN1BAR = { ~IN1 } + IN2BAR = { ~IN2 } + IN3BAR = { ~IN3 } + IN4BAR = { ~IN4 } + IN5BAR = { ~IN5 } + IN6BAR = { ~IN6 } + IN7BAR = { ~IN7 } + IN8BAR = { ~IN8 } + IN9BAR = { ~IN9 } + + D = { IN8 & IN9 } + C = { ~(D & (IN4BAR | IN5BAR | IN6BAR | IN7BAR)) } + B = { ~(D & ((IN2BAR & IN4 & IN5) | + (IN3BAR & IN4 & IN5) | IN6BAR | IN7BAR)) } + A = { ~(IN9BAR | D & ((IN1BAR & IN2 & IN4 & IN6) | + (IN3BAR & IN4 & IN6) | (IN5BAR & IN6) | IN7BAR)) } U147DLY PINDLY (4,0,9) DPWR DGND + A B C D + IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 + A_O B_O C_O D_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATAHI = { IN9=='1 & IN8=='1 & IN7=='1 & IN6=='1 & IN5=='1 & + IN4=='1 & IN3=='1 & IN2=='1 & IN1=='1 } + + PINDLY: + A_O B_O C_O D_O = { + CASE ( + DATAHI, DELAY(-1, 9NS,14NS), + TRN_HL, DELAY(-1, 7NS,11NS), + TRN_LH, DELAY(-1,13NS,19NS), + DELAY(-1,13NS,19NS) + ) + } .ENDS *--------- *$ * 74148 PRIORITY ENCODER 8-3 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74148 IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I + A0_O A1_O A2_O GS_O EO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U148LOG LOGICEXP (9,14) DPWR DGND + IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI + A0 A1 A2 GS EO + D0_GATE IO_STD + IO_LEVEL={IO_LEVEL} + + LOGIC: + IN0 = { IN0_I } + IN1 = { IN1_I } + IN2 = { IN2_I } + IN3 = { IN3_I } + IN4 = { IN4_I } + IN5 = { IN5_I } + IN6 = { IN6_I } + IN7 = { IN7_I } + EI = { EI_I } + IN0BAR = { ~IN0 } + IN1BAR = { ~IN1 } + IN2BAR = { ~IN2 } + IN3BAR = { ~IN3 } + IN4BAR = { ~IN4 } + IN5BAR = { ~IN5 } + IN6BAR = { ~IN6 } + IN7BAR = { ~IN7 } + EIBAR = { ~EI } + + A0 = { ~(EIBAR & ((IN1BAR & IN2 & IN4 & IN6) | + (IN3BAR & IN4 & IN6) | (IN5BAR & IN6) | IN7BAR)) } + A1 = { ~(EIBAR & ((IN2BAR & IN4 & IN5) | + (IN3BAR & IN4 & IN5) | IN6BAR | IN7BAR)) } + A2 = { ~(EIBAR & (IN4BAR | IN5BAR | IN6BAR | IN7BAR)) } + EO = { ~(IN0 & IN1 & IN2 & IN3 & IN4 & IN5 & IN6 & IN7 & EIBAR) } + GS = { ~(EO & EIBAR) } U148DLY PINDLY (5,0,9) DPWR DGND + A0 A1 A2 GS EO + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI + A0_O A1_O A2_O GS_O EO_O + IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATAHI = { IN7=='1 & IN6=='1 & IN5=='1 & IN4=='1 & + IN3=='1 & IN2=='1 & IN1=='1 & IN0=='1 } + ENABLE = { CHANGED(EI,0) } + + PINDLY: + A2_O A1_O A0_O= { + CASE ( + ENABLE, DELAY(-1,10NS,15NS), + DATAHI, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1, 9NS,14NS), + TRN_LH, DELAY(-1,13NS,19NS), + DELAY(-1,13NS,19NS) + ) + } + GS_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1, 8NS,12NS), + ENABLE & TRN_HL, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,18NS,30NS), + TRN_HL, DELAY(-1,14NS,25NS), + DELAY(-1,18NS,30NS) + ) + } + EO_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,10NS,15NS), + ENABLE & TRN_HL, DELAY(-1,17NS,30NS), + TRN_LH, DELAY(-1, 6NS,10NS), + TRN_HL, DELAY(-1,14NS,25NS), + DELAY(-1,17NS,30NS) + ) + } .ENDS *--------- *$ * 74151A MULTIPLEXER/DATA SELECTOR 8-1 LINE * * THE TTL DATA BOOK, 1988, TI * TC 08/20/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES .SUBCKT 74151A GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U151ALOG LOGICEXP(12,14) DPWR DGND + GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 W Y + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + IG = { ~GBAR } + ID0 = { D0 & IA & IB & IC & IG } + ID1 = { D1 & A & IB & IC & IG } + ID2 = { D2 & IA & B & IC & IG } + ID3 = { D3 & A & B & IC & IG } + ID4 = { D4 & IA & IB & C & IG } + ID5 = { D5 & A & IB & C & IG } + ID6 = { D6 & IA & B & C & IG } + ID7 = { D7 & A & B & C & IG } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } + Y = { ~W } U151ADLY PINDLY(2,0,12) DPWR DGND + W Y + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O Y_O + IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y_O = { + CASE( + SELECT, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,21NS,33NS), + ENABLE & TRN_HL, DELAY(-